A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

Abstract

Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range, with a predefined modulation profile.We present the implementation of an all-digital spread spectrum clock generator. The circuit is realized by using a design flow completely based on standard cells and is able to perform clock spreading with an arbitrary modulation profile and a modulation frequency up to 5 MHz. The circuit uses two digitally controlled delay lines driven by a digital modulator to synthesize the output waveform. A replica delay line is employed in a real-time measurement circuit to track process, voltage and temperature variations.A chip has been implemented in a 65 nm CMOS technology. The chip is able to generate signals up to 1.27 GHz. The measured peak level reduction of the clock spectrum, at 750 MHz output frequency, is 20.5 dB with a 6% modulation depth. The power dissipation is 44 mW @ 1.27 GHz.Index Terms-Clock synthesis, digitally controlled delay line, EMI reduction, spread-spectrum clock generator (SSCG).

Analysis of Digitally Controlled Delay Loop-Nand Gate For Glitch Free Design

“…DCDL plays an important role in many applications such as All-Digital Phase Locked Loop (ADPLL) [3], All Digital Delay Locked Loop (ADDLL) [4], [5], All Digital Spread-Spectrum Clock Generator (SSCG) [2], Clock Generators, microprocessors etc.…”

A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS

“…There are many efforts to reduce the EMI, and among these EMI solutions, the spread spectrum clock generator (SSCG) is the most effective. Recently, many types for SSCG have been reported [1,2,3,4]. The direct modulation on a voltage controlled oscillator (VCO) based SSCG [1] usually makes better EMI reduction performance than other modulation methods.…”

“…Therefore, as shown in [2], the measured modulation profile is more close to a sinusoidal modulation profile, and then the EMI reduction is reduced due to the peak power occurs at certain frequencies. In order to disperse peak power averagely, the Hershey-kiss modulation is adopted with a digitally controlled delay-line (DCDL) cascaded with a PLL [4]. This approach can perform sharper modulation profile on both side of frequency domain.…”

“…Nevertheless, the Hershey-kiss modulation is a very complicated profile, and it may require an extra memory space to perform the profile. Moreover, the DCDL [4] receives the clock from PLL, and thus, it operates at a higher frequency which results in high power consumption. This phenomenon will make this architecture become more complex and will increase the design complexity of the SSCG.…”

A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile

“…Therefore a better EMI peak reduction could be achieved with HersheyKiss modulation profile [2]. Conventionally the HersheyKiss profile modulator is implemented by read-onlymemory (ROM) [3]. In prior works the Hersey-Kiss profile or Hersey-Kiss-like profile was generated by look-up-table (LUT) [2], SRAM [3], piecewise linear modulation [4], and a Newton-Raphson method design [5].…”