A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

Bae, Young‐Seuk; Park, Joon‐Young; Rhee, Sang Jae; Ko, Seung Bum; Jeong, Young Gyu; Noh, Kwang-Sook; Son, Younghoon; Youn, Jaeyoun; Yong-Gyu, Chu; Cho, Hyunyoon; Kim, Mi-Jo; Yim, Dae-Sik; Kim, Hyochang; Jung, Sungjune; Choi, Hye-In; Yim, S.-M.; Lee, Jung-Bae; Choi, Jongwan; Oh, Kyungseok

doi:10.1109/isscc.2012.6176871

Cited by 17 publications

(7 citation statements)

References 2 publications

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“…In the author's best knowledge and reference, the 3D PAM I/O is never reported before and would be first analyzed. [36] using 22nm technology achieves better energy efficiency, the proposed energy efficiency of proposed 4-PAM transceiver is better (1.67pJ/b/pin) than other technologies' works [27], [31], [33][34][35]. This 3D PAM level can be further extended to more levels in the future, such that multiple data streams can be transceived through a shared I/O interface and generate much improved energy efficiency.…”

Section: Resultsmentioning

confidence: 97%

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An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs

Jalalifar

2014

Fifteenth International Symposium on Quality Electronic Design

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This paper presents a four-level pulse amplitude modulation (4-PAM) memory I/O interface for 3D stacked DRAMs. 3D integration technology is a promising solution for higher bandwidth and less power consumption due to the shortened link distance. The proposed transceiver is designed for 3D interconnects. The proposed transmitter employs a current mode output driver which sends data through TSVs. The receiver side uses differential amplifiers to decode three voltage levels by comparing the PAM signal with three reference voltages. The proposed scheme is simulated in 40 nm CMOS technology at 1.0 V. We use a highly accurate 3D electromagnetic (EM) simulator such as HFSS for 3D TSV channels simulations. The proposed architecture reduces the power consumption compared with prior works. It also increases the data bandwidth to 6.4 Gb/s/pin. Energy efficiency of proposed 3D mobile PAM I/O memory interface is 1.7 pJ/bit/pin.

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Section: Resultsmentioning

confidence: 97%

“…For example, commodity low-power DDR (LP-DDR2) operates at 0.8Gb/s/pin and current LP-DDR3 operates at 1.6Gb/s/pin with 3.7 pJ/bit/pin [27]. We first analyze and design the 3D DRAM PAM interface with 3D stacked multi-drop bus architecture.…”

Section: D Pam Mobile Memory Architecturementioning

confidence: 99%

An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs

Jalalifar

2014

Fifteenth International Symposium on Quality Electronic Design

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“…In response to the growing demand for high-performance DRAM, the interface in LPDDR3 now supports termination [2], [12]. The performance target of LPDDR4 standard, however, cannot be satisfied with the conventional interface scheme, and thus adopts a small swing interface called low-voltage-swing terminated logic (LVSTL) with VSSQ termination.…”

Section: B Lvstl Interfacementioning

confidence: 99%

“…At the introduction of the first mobile DRAM standard (LPDDR), the required pin bandwidth was 400 Mbps with 1.8 V supply voltage [1]. LPDDR2 devices operated at 1066 Mbps/pin at 1.2 V, and LPDDR3 at 2133 Mbps/pin [2], [11]. Recently, DRAM with wide IO has been reviewed as the candidate for the next generation device for mobile application.…”

Section: Introductionmentioning

confidence: 99%

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

Song

Lee

Kim

et al. 2015

IEEE J. Solid-State Circuits

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The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

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“…DDR3-1333 [36] 10.7 2GB DDR4-2667 [36] 21.3 2GB LPDDR3 (30nm) [4] 6.4 512MB HMC I (3D-Stack) [36] 128.0 512MB Wide I/O (3D-stack, 50nm) [25] 12.8 512MB Tezzaron Octopus (3D-Stack) [1] 50.0 512MB Future Tezzaron (3D-stack) [14] 100.0 4GB drives provide up to 20× the capacity per server and still supports tens of thousands of operations per second. This prompted the creation of McDipper, a Flash-based cache server that is compatible with Memcached.…”

Section: Dram Bw (Gb/s) Capacitymentioning

confidence: 99%

Integrated 3D-stacked server designs for increasing physical density of key-value stores

Gutierrez

Cieslak

Giridhar

et al. 2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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Key-value stores, such as Memcached, have been used to scale web services since the beginning of the Web 2.0 era. Data center real estate is expensive, and several industry experts we have spoken to have suggested that a significant portion of their data center space is devoted to key-value stores. Despite its wide-spread use, there is little in the way of hardware specialization for increasing the efficiency and density of Memcached; it is currently deployed on commodity servers that contain high-end CPUs designed to extract as much instruction-level parallelism as possible. Out-oforder CPUs, however have been shown to be inefficient when running Memcached.To address Memcached efficiency issues, we propose two architectures using 3D stacking to increase data storage efficiency. Our first 3D architecture, Mercury, consists of stacks of ARM Cortex-A7 cores with 4GB of DRAM, as well as NICs. Our second architecture, Iridium, replaces DRAM with NAND Flash to improve density. We explore, through simulation, the potential efficiency benefits of running Memcached on servers that use 3D-stacking to closely integrate low-power CPUs with NICs and memory. With Mercury we demonstrate that density may be improved by 2.9×, power efficiency by 4.9×, throughput by 10×, and throughput per GB by 3.5× over a state-of-the-art server running optimized Memcached. With Iridium we show that density may be increased by 14×, power efficiency by 2.4×, and throughput by 5.2×, while still meeting latency requirements for a majority of requests.

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A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

Cited by 17 publications

References 2 publications

An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs

An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

Integrated 3D-stacked server designs for increasing physical density of key-value stores

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