In this paper, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines (DCDLs) in a shared digital feedback loop with a time-multiplexed loop filter, so as to minimize the effect of circuit mismatch that hampers the phase accuracy. A self-calibrated offset delay is also proposed that allows the use of a simple 1-bit TDC instead of a power hungry wide-dynamic range TDC. Implemented in 65nm CMOS, the prototype chip achieves less than 1.1ps phase error for 1.25GHz quadrature signal and occupies an active area of only 0.01mm 2 while consuming 2.27mW from a 1.0V supply.Index Terms-Quadrature clock signal corrector, digitallycontrolled delay line(DCDL), bang-bang phase detector(BBPD), time-multiplexed loop filter.

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The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

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