A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

Lee, Hyun–Woo; Wang, Yun; Choi, Young-Kyoung; Choi, Hyang-Hwa; Lee, Jong-Jin; Kim, Ki-Han; Kang, Shin-Deok; Yang, Ji-Yeon; Kang, Jae-Suck; Lee, Hyeng-Ouk; Dong-Uk, Lee; Sim, Su-Jeong; Kim, Young‐Ju; Choi, Won-Jun; Song, Keunsoo; Shin, Sanghoon; Moon, Hyung-Wook; Kwack, Seung-Wook; Lee, Jungwoo; Park, Nak-Kyu; Kim, Kwan-Weon; Choi, Young-Jung; Ahn, Ji Hoon; Chung, Byong-Tae

doi:10.1109/isscc.2009.4977347

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2013

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“…studies have been carried out to achieve an optimal tradeoff between these two objectives. Among these studies, DVS is one of the most widely applied techniques [128][129][130][131][132][133][134][135]. With DVS, the energy dissipation can be reduced substantially by scaling down the supply voltage when the operating workload is low.…”

Section: Resultsmentioning

confidence: 99%

Design methodologies for robust and low-overhead asynchronous quasi-delay-insensitive digital systems

Zhou¹

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In the past decades of electronic circuit designs, the synchronous-logic (sync) is the main de-facto design approach for digital systems. This is largely due to its synchronization to a global clock signal (or its variants thereof) which simplifies the data transfer. Nevertheless, designing digital circuits and systems based on sync approach is becoming more challenging due to the increase in process, voltage and temperature (PVT) variations in the deep submicron fabrication process. An alternative design approach which is based on the asynchronous-logic (async), is

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