In this paper, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines (DCDLs) in a shared digital feedback loop with a time-multiplexed loop filter, so as to minimize the effect of circuit mismatch that hampers the phase accuracy. A self-calibrated offset delay is also proposed that allows the use of a simple 1-bit TDC instead of a power hungry wide-dynamic range TDC. Implemented in 65nm CMOS, the prototype chip achieves less than 1.1ps phase error for 1.25GHz quadrature signal and occupies an active area of only 0.01mm 2 while consuming 2.27mW from a 1.0V supply.Index Terms-Quadrature clock signal corrector, digitallycontrolled delay line(DCDL), bang-bang phase detector(BBPD), time-multiplexed loop filter.