A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS

Yeoh, Hong Chang; Jung, Jae-Hun; Jung, Yun-Hwan; Baek, Kwang‐Hyun

doi:10.1109/jssc.2010.2056830

Cited by 45 publications

(14 citation statements)

References 24 publications

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“…The accumulator could be extended to be 48-bit when a high resolution DDFS is required. 0.25 m CMOS [3] 90 nm CMOS [4] InP DHBT [10] SiGe HBT [11] GaAs HBT (This work) …”

Section: Resultsmentioning

confidence: 99%

“…However, the operating speed of DDFS is limited by the phase accumulator (PA), which consumes large area and power. Many architectures and designs have been reported in the literature for the PA in DDFS, such as the carry-ripple adder (RCA) [1], the carry look ahead adder (CLA) [2] and the pipelined adder [3,4]. Though faster than RCA, the significant fan-in and fan-out requirements of CLA architecture lead to lower clock rate as the bit width increases.…”

mentioning

confidence: 99%

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A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

Chen

Zhou

et al. 2012

Chin. Sci. Bull.

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A 32-bit pipeline accumulator with carry ripple topology is implemented for direct digital frequency synthesizer. To increase the throughout while hold down the area and power consumption, a method to reduce the number of the pre-skewing registers is proposed. The number is reduced to 29% of a conventional pipeline accumulator. The propagation delay versus bias current of the adder circuit with different size transistors is investigated. We analyze the delay by employing the open circuit time constant method. Compared to the simulation results, the maximum error is less than 8%. A method to optimum the design of the adder based on the propagation delay is discussed. The clock traces for the 32-bit adder are heavily loaded, as there are 40 registers being connected to them. Moreover, the differential clock traces, which are much longer than the critical length, should be treated as transmission lines. Thus a clock distribution method and a termination scheme are proposed to get high quality and low skew clock signals. A multiple -type termination scheme is proposed to match the transmission line impedance. The 32-bit accumulator was measured to work functionally at 5.3 GHz. Direct digital frequency synthesizer (DDFS) is able to generate sinusoids with sub-hertz resolution, good spectral purity, fast frequency switching and phase continuity on switching. For the next generation radar and communication systems, DDFS operating at GHz-range clock is required. However, the operating speed of DDFS is limited by the phase accumulator (PA), which consumes large area and power. Many architectures and designs have been reported in the literature for the PA in DDFS, such as the carry-ripple adder (RCA) [1], the carry look ahead adder (CLA) [2] and the pipelined adder [3,4]. Though faster than RCA, the significant fan-in and fan-out requirements of CLA architecture lead to lower clock rate as the bit width increases. The pipeline accumulator offers significant speed improvement compared to the CLA, which has large propagation delays before a valid sum is produced. The carry ripple pipeline accumulator is more practically suitable for GHz DDFS with 32-bit resolution in terms of compact layout and hardware implementation. A 32-bit pipeline accumulator with 8-stage pipeline is illustrated in Figure 1. A number of pre-skewing and deskewing registers are required to keep the input and output of the accumulator coherent. To minimize the area while achieving the desired operating speed, a new hardware efficient PA is proposed in this work. This method reduces the number of registers required in the pipeline without performance degradation. The optimum design in terms of power and propagation delay is investigated. The clock for the accumulator is critical for high speed operation. A clock distribution method and a termination scheme are proposed.

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“…The accumulator could be extended to be 48-bit when a high resolution DDFS is required. 0.25 m CMOS [3] 90 nm CMOS [4] InP DHBT [10] SiGe HBT [11] GaAs HBT (This work) …”

Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

Chen

Zhou

et al. 2012

Chin. Sci. Bull.

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“…In high-speed DDFSs, the most of PACCs adopt a pipelined structure to resolve the speed bottleneck in carry propagation [1]. Fig.…”

Section: Previous Pipelined Paccsmentioning

confidence: 99%

“…Direct digital frequency synthesizers (DDFSs) play an important role in modern digital communications for having many significant advantages over traditional phase-locked loops such as fine frequency resolution, wide tuning bandwidth, and fast frequency switching performance [1,2,3]. However, high-power consumption is one of drawbacks of DDFS for monolithic microwave integrated circuit (MMIC) applications (>5 GHz) [2].…”

Section: Introductionmentioning

confidence: 99%

“…Among these basic building blocks, P2AM has been the most power-hungry block due to complex digital circuitry and a large number of D-flop/flops (F/Fs) [4,5]. However, the recent DDFS developments work towards simplifying the complexity of P2AM blocks and thereby reducing the power consumption, which leads to increased power in PACC relatively [1,2,3]. Therefore, the power reduction in PACC blocks can be significant achievement in designing a low-power DDFS [3,4,5].…”

Section: Introductionmentioning

confidence: 99%

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Low-power pipelined phase accumulator using CMOS-CML hybrid F/Fs for pre-skewing operation

Jung

Kim

Hong

et al. 2013

IEICE Electron. Express

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Abstract:In this paper, a low-power pipelined phase accumulator (PACC) for high-speed direct digital frequency synthesizers (DDFSs) is presented. In the proposed PACC structure, the accumulator core block and the post-skewing block are based on current mode logic (CML) design topology for high-speed operations, whereas the preskewing block consists of static CMOS D-F/Fs and CMOS-CML hybrid F/Fs for low-power operations. The proposed CMOS-CML hybrid F/F provides fast level conversion (CMOS to CML) by having separate current sources and it also consumes low power dissipation by sequentially activating the current sources. Simulated results show that the proposed 24-bit PACC reduces power consumption by 31% compared with a conventional pipelined architecture when input data is updated every eight clock cycles. The operating speed of the proposed PACC is 45% faster than that of the conventional pipelined PACC under the condition of the same power dissipation.

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Phase to Amplitude Converter

Zhang

Zhang²,

2022

High-Speed and High-Performance Direct Digital Frequency Synthesizer Design

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A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS

Cited by 45 publications

References 24 publications

A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

Low-power pipelined phase accumulator using CMOS-CML hybrid F/Fs for pre-skewing operation

Phase to Amplitude Converter

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