A 1.3-GHz fifth-generation SPARC64 microprocessor

Ando, Hironori; Yoshida, Yoshitoku; Inoue, Akira; Sugiyama, I.; Takeo, Asakawa; Morita, K.; Muta, T.; Motokurumada, Tsuyoshi; Okada, Seishi; Yamashita, Hideo; Satsukawa, Y.; Konmoto, Akihiko; Yamashita, Ryohei; Sugiyama, Hiroyuki

doi:10.1109/jssc.2003.818146

Cited by 87 publications

(43 citation statements)

References 12 publications

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“…A major benefit of coarser recovery mechanisms is that some form of checkpointrecovery is already shipping in today's systems [30], [32] for soft-error tolerance. Moreover, newer applications are emerging that leverage and re-use this general-purpose hardware for tasks such as debugging, testing, etc.…”

Section: B Designing For Typical-case Operationmentioning

confidence: 99%

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Reddi

Kanev

Kim

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel R Core TM 2 Duo processor. By sensing on-die voltage as the processor runs singlethreaded, multi-threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4%, far from the processor's 14% worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15% to 20% performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing microarchitectural activity that leads to voltage swings within multi-core systems, we show that a voltagenoise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.

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Section: B Designing For Typical-case Operationmentioning

confidence: 99%

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Reddi

Kanev

Kim

et al. 2010

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture

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“…By copying fetched instructions to generate the redundant threads, any transient faults which would happen inside the I-Cache might not be detected. However, ECC-like mechanisms that are very effective in handling transient faults in memory structures are now widely implemented in modern microprocessors [7,31,10]. Further, the fault which occurs in the BPUs will have no effect on the ultimate correct program execution [32], whereas the critical component PCs must be protected by ECC-like mechanisms.…”

Section: Lowering the Performance Overhead Of Transient Fault-toleranmentioning

confidence: 99%

“…10 As we have seen, each instruction fetched is associated with a sequential number at first, then the fetched instruction is replicated to generate the redundant thread. In doing this, two copied instructions will have the same sequential numbers in different threads.…”

Section: Preventing the Dispatch Of Tt Wrong-path Instructionsmentioning

confidence: 99%

“…In order to handle these inevitable errors, we must integrate in our design fault-tolerant features so that processors can continue to correctly perform their specified tasks despite the occurrence of logic errors [5]. Such designs as the Intel Itanium [6,7], the IBM Power6 [8], the z10 [9], the Fujitsu SPARC64 [10], etc., already include transient fault detection and recovery mechanisms.…”

Section: Introductionmentioning

confidence: 99%

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Tolerating Radiation-Induced Transient Faults in Modern Processors

Gaudiot

2009

Int J Parallel Prog

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As MOS device sizes continue shrinking, lower charges, for example those charges carried by single ionizing particles of naturally occurring radiation, are sufficient to upset the functioning of complex modern microprocessors. In order to handle these inevitable errors, designs should include fault-tolerant features so that the processors can continue to correctly perform despite the occurrence of errors. The main goal of this work is to develop architecture mechanisms to protect processors against the effect of such radiation-induced transient faults. It should first be noted that, from a program execution perspective, many faults manifest themselves as control flow errors that cause processors to violate the correct sequencing of instructions. We present here at first a basic compile-time signature assignment algorithm and describe a novel approach to improve the fault detection coverage of the basic algorithm. Moreover, to allow the processor to efficiently check the run-time sequence and detect control flow errors, we introduce an on-chip assigned-signature checker which is capable of executing three additional instructions (SIC, SIJ, SIJC). Second, since the very concept of simultaneous multi-threading (SMT) provides the necessary redundancy, some proposals have been made to run two copies of the same thread on top of SMT platforms in order to detect and correct soft errors. This allows, upon detection of an error, the rolling back of the processor state to a known safe point, and then a retry of the instructions, thereby effecting a completely error-free execution. This paper has focused on two crucial implementation issues introduced by this

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“…In the future, these errors will become especially troublesome, particularly for exascale systems comprising up to millions of commodity cores [4]. To address this problem, architects have proposed hardware enhancements (ranging from buses [5], to on-chip memory [2], [5], pipelines [6], and functional units [5], [7]). Unfortunately, introducing dedicated hardware requires both time and effort, and this approach may not be feasible for low-volume, emerging architectures.…”

Section: Introductionmentioning

confidence: 99%

ROSE::FTTransform - A source-to-source translation framework for exascale fault-tolerance research

Lidman

Quinlan

Liao

et al. 2012

IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN 2012)

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Abstract-Exascale computing systems will require sufficient resilience to tolerate numerous types of hardware faults while still assuring correct program execution. Such extreme-scale machines are expected to be dominated by processors driven at lower voltages (near the minimum 0.5 volts for current transistors). At these voltage levels, the rate of transient errors increases dramatically due to the sensitivity to transient and geographically localized voltage drops on parts of the processor chip. To achieve power efficiency, these processors are likely to be streamlined and minimal, and thus they cannot be expected to handle transient errors entirely in hardware. Here we present an open, compiler-based framework to automate the armoring of High Performance Computing (HPC) software to protect it from these types of transient processor errors. We develop an open infrastructure to support research work in this area, and we define tools that, in the future, may provide more complete automated and/or semi-automated solutions to support software resiliency on future exascale architectures. Results demonstrate that our approach is feasible, pragmatic in how it can be separated from the software development process, and reasonably efficient (0% to 30% overhead for the Jacobi iteration on common hardware; and 20%, 40%, 26%, and 2% overhead for a randomly selected subset of benchmarks from the Livermore Loops [1]).

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A 1.3-GHz fifth-generation SPARC64 microprocessor

Cited by 87 publications

References 12 publications

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Tolerating Radiation-Induced Transient Faults in Modern Processors

ROSE::FTTransform - A source-to-source translation framework for exascale fault-tolerance research

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