Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling

Abstract

Abstract-Parameter variations have become a dominant challenge in microprocessor design. Voltage variation is especially daunting because it happens so rapidly. We measure and characterize voltage variation in a running Intel R Core TM 2 Duo processor. By sensing on-die voltage as the processor runs singlethreaded, multi-threaded, and multi-program workloads, we determine the average supply voltage swing of the processor to be only 4%, far from the processor's 14% worst-case operating voltage margin. While such large margins guarantee correctness, they penalize performance and power efficiency. We investigate and quantify the benefits of designing a processor for typical-case (rather than worst-case) voltage swings, assuming that a fail-safe mechanism protects it from infrequently occurring large voltage fluctuations. With today's processors, such resilient designs could yield 15% to 20% performance improvements. But we also show that in future systems, these gains could be lost as increasing voltage swings intensify the frequency of fail-safe recoveries. After characterizing microarchitectural activity that leads to voltage swings within multi-core systems, we show that a voltagenoise-aware thread scheduler in software can co-schedule phases of different programs to mitigate error recovery overheads in future resilient processor designs.

Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors

“…To account for these factors, microprocessor designers add large guardbands to the V dd . These guardbands, which can be as high as 20% [13,22] in modern processors, make microprocessors less energy efficient.…”

Performance boosting under reliability and power constraints

“…A number of papers dealt with mitigating voltage droops using software techniques [4][5] [16]. These techniques recognize the existence of repetitive code with high di/dt transition activity and dampen or eliminate this activity through software techniques.…”

“…However, standard applications running under normal conditions do not exhibit voltage variations anywhere close to the worst-case margins [10]. Guarding against worst-case scenarios can significantly or disproportionally decrease performance; for instance, according to [16], a 20% voltage margin translates into a 33% frequency loss.…”

Active management of timing guardband to save energy in POWER7

“…Reddi et al [18] study voltage margin in an Intel Core 2 Duo processor and suggest scheduling algorithms to reduce voltage droop events. They also present a good overview of voltage margin.…”

“…The timing margin for circuits in the microprocessor is affected by manufacturing process, thermal fluctuation, frequency changes, voltage slewing, and aging. Selecting an operating voltage that is high enough to account for worst-case conditions, without violating power budgets and thereby limiting performance, is a growing challenge [18].…”