A 1.3-ns 32-word×32-bit three-port BiCMOS register file

This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36*37 mu m/sup 2/ using a 0.6- mu m technology. An experimental 32 word * 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word*4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 mu A/cell when operated at 1 V

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A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file

Hwang

Joshi²,

Henkels³

1999

IEEE J. Solid-State Circuits

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A 1.3-ns 32-word×32-bit three-port BiCMOS register file

Cited by 9 publications

References 8 publications

A Novel Adiabatic Register File Design

A Novel Adiabatic Register File Design

A new low-power GaAs two-single-port memory cell

A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file

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