A 1.3GHz fifth generation SPARC64 microprocessor

Ando, Hironori; Yamashita, Hideo; Satsukawa, Y.; Konmoto, Akihiko; Yamashita, Ryouichi; Sugiyama, Hiroyuki; Yoshida, Yoshitoku; Sugiyama, I.; Asakawa, Takeo; Morita, K.; Muta, Toshiyuki; Motokurumada, Tsuyoshi; Okada, Seishi

doi:10.1145/776008.776010

Cited by 4 publications

(1 citation statement)

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“…HP NonStop series processors [5] are designed in TMR (triple-modular redundancy) and hardware voters guarantee the correct execution of the program. In Power 6 [21] and in Fujitsu's SPARC64 [3], they use parity and residue checking to protect their systems against transient errors.…”

Section: Speed Up Factorsmentioning

confidence: 99%

CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

Mitropoulou

Porpodas

Cintra

2013

2013 IEEE 27th International Symposium on Parallel and Distributed Processing

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Abstract-Aggressive silicon process scaling over the last years has made transistors faster and less power consuming. Meanwhile, transistors have become more susceptible to errors. The need to maintain high reliability has led to the development of various software-based error detection methodologies which target either single-core or multi-core processors.In this work, we present CASTED, a Core-Adaptive Software Transient Error Detection methodology that focuses on improving the impact of error detection overhead on singlechip scalable architectures that are composed of tightly coupled cores. The proposed compiler methodology adaptively distributes the error detection overhead to the available resources across multiple cores, fully exploiting the abundant ILP of these architectures. CASTED adapts to a wide range of architecture configurations (issue-width, inter-core delay).We evaluate our technique on a range of architecture configurations using the MediabenchII video and SPEC CINT2000 benchmark suites. Our approach successfully adapts to (and regularly outperforms by up to 21.2%) the best fixed state-ofthe-art approach while maintaining the same fault coverage.

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Section: Speed Up Factorsmentioning

confidence: 99%

CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

Mitropoulou

Porpodas

Cintra

2013

2013 IEEE 27th International Symposium on Parallel and Distributed Processing

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Tolerating Radiation-Induced Transient Faults in Modern Processors

Gaudiot

2009

Int J Parallel Prog

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As MOS device sizes continue shrinking, lower charges, for example those charges carried by single ionizing particles of naturally occurring radiation, are sufficient to upset the functioning of complex modern microprocessors. In order to handle these inevitable errors, designs should include fault-tolerant features so that the processors can continue to correctly perform despite the occurrence of errors. The main goal of this work is to develop architecture mechanisms to protect processors against the effect of such radiation-induced transient faults. It should first be noted that, from a program execution perspective, many faults manifest themselves as control flow errors that cause processors to violate the correct sequencing of instructions. We present here at first a basic compile-time signature assignment algorithm and describe a novel approach to improve the fault detection coverage of the basic algorithm. Moreover, to allow the processor to efficiently check the run-time sequence and detect control flow errors, we introduce an on-chip assigned-signature checker which is capable of executing three additional instructions (SIC, SIJ, SIJC). Second, since the very concept of simultaneous multi-threading (SMT) provides the necessary redundancy, some proposals have been made to run two copies of the same thread on top of SMT platforms in order to detect and correct soft errors. This allows, upon detection of an error, the rolling back of the processor state to a known safe point, and then a retry of the instructions, thereby effecting a completely error-free execution. This paper has focused on two crucial implementation issues introduced by this

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DAFT: Decoupled Acyclic Fault Tolerance

Zhang

Lee

Johnson

et al. 2011

Int J Parallel Prog

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Higher transistor counts, lower voltage levels, and reduced noise margin increase the susceptibility of multicore processors to transient faults. Redundant hardware modules can detect such errors, but software transient fault detection techniques are more appealing for their low cost and flexibility. Recent software proposals double register pressure or memory usage, or are too slow in the absence of hardware extensions, preventing widespread acceptance. This paper presents DAFT, a fast, safe, and memory efficient transient fault detection framework for commodity multicore systems. DAFT replicates computation across multiple cores and schedules fault detection off the critical path. Where possible, values are speculated to be correct and only communicated to the redundant thread at essential program points. DAFT is implemented in the LLVM compiler framework and evaluated using SPEC CPU2000 and SPEC CPU2006 benchmarks on a commodity multicore system. Results demonstrate DAFT's high performance and broad fault coverage. Speculation allows DAFT to reduce the performance overhead of software redundant multithreading from an average of 200% to 38% with no degradation of fault coverage.

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A 1.3GHz fifth generation SPARC64 microprocessor

Cited by 4 publications

References 0 publications

CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores

Tolerating Radiation-Induced Transient Faults in Modern Processors

DAFT: Decoupled Acyclic Fault Tolerance

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