A 1.4V 10b CMOS DC DAC in 0.01mm/sup 2/

Abstract

0 . 1 8~ CMOS process. The DAC is optimized for circuit calibration in large ASICs and occupies 0.01034 mm' (1 IOW x 9 4~) of die area. Creative layout and current mirroring techniques are implemented to minimize area while providing output current with sufficient headroom. The measured DNLfiNL is better than 0.7/0.75 LSB and OH2 LSB for 1.8V and 1.4V power supplies, respectively. The DAC consumes 3.96mW at 1.8V and 3.08mW at 1.4V.