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This paper presents a novel 1.8 V digital-to-analog converter (DAC) which is designed to operate at DC for a wide variety of circuit calibration techniques. To achieve 10-bit performance at 1.8 V, an ultra high gain op-amp is introduced for servoing. In order to minimize area consumption while maximizing performance, a segmented plus binary plus R-2R architecture is used. The DAC was designed in a standard digital 0.18 p m CMOS process. The DAC occupies 0.0143 mm2 (110 p m x 130 pm), and consumes 2.8 mW of power. The 5 stage cascaded op-amp with feedforward compensation achieves 130 dB of gain with 81" phase margin while consuming only 60 pW.

0 . 1 8~ CMOS process. The DAC is optimized for circuit calibration in large ASICs and occupies 0.01034 mm' (1 IOW x 9 4~) of die area. Creative layout and current mirroring techniques are implemented to minimize area while providing output current with sufficient headroom. The measured DNLfiNL is better than 0.7/0.75 LSB and OH2 LSB for 1.8V and 1.4V power supplies, respectively. The DAC consumes 3.96mW at 1.8V and 3.08mW at 1.4V.