A 1.8 V CMOS DAC cell with ultra high gain op-amp in 0.0143 mm/sup 2/

Abstract

This paper presents a novel 1.8 V digital-to-analog converter (DAC) which is designed to operate at DC for a wide variety of circuit calibration techniques. To achieve 10-bit performance at 1.8 V, an ultra high gain op-amp is introduced for servoing. In order to minimize area consumption while maximizing performance, a segmented plus binary plus R-2R architecture is used. The DAC was designed in a standard digital 0.18 p m CMOS process. The DAC occupies 0.0143 mm2 (110 p m x 130 pm), and consumes 2.8 mW of power. The 5 stage cascaded op-amp with feedforward compensation achieves 130 dB of gain with 81" phase margin while consuming only 60 pW.