A 1.5 V BiCMOS dynamic logic circuit using a "BiPMOS pull-down" structure for VLSI implementation of full adders

Abstract

Theory and practical implementation of a fifth-order sigma-delta A/D converter," Audio Eng.

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

“…For example, @0.25 pF load, the ETD is maximum for M ETER @PMOS1(original structure in Ref. [5]) where the source potential of the M ETER is at the apex (refer to Fig. 2(a)) of the potential slope(requiring the largest VGS transition to turn off the M ETER ) and the least for M ETER @PMOS5 where the source potential of the M ETER is at almost the bottom (refer to Fig.…”

“…[4] provided a closed form design optimization through transistor reordering for minimum expected dynamic power dissipation in the internal nodes of the MOSFET chain of a CMOS NAND gate. In this paper, we have focused on the dynamic BiCMOS logic gates (reported by several authors, [5,7,9]), and, have proposed improved transistor reordered structures based on a deterministic (rather than probabilistic) power dissipation measure. Small reduction in the gate delay-time is also achieved by this transistor reordering.…”

“…which has a precharge cycle during the clock low period and an evaluation cycle during the clock high period as discussed in Ref. [5] (henceforth this circuit is referred to as the Kuo structure). The NPN Q1 is turned off at the end of logic evaluation (switching off dynamic power dissipation) via output transient feedback to the gate of the PMOS Evaluation TERminator device M ETER .…”

A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation

“…The speed performance of a CPU is predominantly determined by its adder circuit. Various adder circuits with improved speed performance have been reported [1]- [8]. Among them, the conditional carry select (CCS) adder [1] has a superior speed performance.…”

“…if if (7) In the fifth carry block, six output carry signals -are produced if if (8) As shown in the figure, in the SICNB CCS adder, the number of output carry signals produced in each block is successively incremented from the first block to the last block. The longest critical path is from to , which occurs at inputs ; , which involves gate delays of six stages-one stage of or and five stages of multiplexers.…”