A 1.5 v High Swing Ultra-Low-Power Two Stage CMOS OP-AMP in 0.18 &amp;#x00B5;m Technology

Kargaran, Ehsan; Khosrowjerdi, Hojat; Ghaffarzadegan, Karim

doi:10.1109/icmee.2010.5558594

Cited by 12 publications

(5 citation statements)

References 9 publications

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“…The phase margin is an ideal measure of the transient response in an amplifier and it is obtained from the poles and zeroes of the amplifier's transfer function (Kargaran et al 2010;Yang and Juntang 2009). While, the dominant pole (⍵ p1 ) in IRFC is located at the output node, the nondominant pole (⍵ p2 ) of IRFC is decided by the parasitic capacitances present at the source nodes of N9 and N10.…”

Section: Phase Marginmentioning

confidence: 99%

Design of a power efficient, high slew rate and gain boosted improved recycling folded cascode amplifier with adaptive biasing technique

SarkarArnab

Shatakshi

2016

Microsyst Technol

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As technology scaling progresses, the intrinsic gain of the transistor reduces, thereby making the design of Operational Transconductance Amplifiers a very challenging process (Vij et al. 2014). This reliability issue in deep submicron technologies has affected the output swing of the operational amplifiers when operated at lower supply voltages. Hence, arises the need of designing high gain, high slew rate and power efficient amplifiers with a reasonably large output swing.In order to enhance the DC gain and reduced ouput swing of the single stage amplifiers, multi stage amplifiers are preferred. These amplifiers are equipped with three or more stages and often use Nested Miller-Compensation technique which improves the gain significantly but requires the usage of additional compensation capacitors which not only consumes larger die area but also limits the slew rate. A desirable approach would be to use common mode feedback circuits but they have a limitation of additional power consumption.In sub-micron CMOS processes, folded cascode amplifiers are considered to be the most preferred architectures which can achieve a higher DC gain and output swing even at lower supply voltages. An added advantage of using folded cascode amplifier implemented with PMOS input pair instead of its NMOS counterpart is the presence of higher dominant poles and reduced flicker noise levels. But the only drawback of this configuration is that even if the gain is high, it is not sufficient for high settling accuracy. Moreover, the choice comes at the expense of an increase in input capacitance and power. A number of techniques to enhance the DC gain in OTAs have been discussed in literature. One of these techniques demonstrates gain enhancement when an additional current path is provided at the cascode node.Abstract This paper presents an adaptive Improved Recycling Folded Cascode (IRFC) amplifier with improved gain, high slew rate, high phase margin and reduced power consumption. The proposed design is implemented using 180 nm technology with a supply voltage of 1.8 V and a capacitive load of 1 pF. The proposed design is compared with basic two stage op-amp, cascode amplifier and conventional recycling folded cascode amplifier (RFC). Analysis demonstrates that the flexible structure of IRFC with adaptive biasing shows an improvement in gain to 87.74 dB, approximately three times enhancement in slew rate to 53.8 V/µs when compared with the design specifications. The phase margin was observed to be 64.86°. The design also reports an increase in output swing. The gain increases to 109 dB when a cascode stage is added to the IRFC structure.

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Section: Phase Marginmentioning

confidence: 99%

Design of a power efficient, high slew rate and gain boosted improved recycling folded cascode amplifier with adaptive biasing technique

SarkarArnab

Shatakshi

2016

Microsyst Technol

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“…Ehsan Kargaran et al [9] approached the cascade technique to increase the dc gain and miller capacitor feedback path to enhance the unity gain bandwidth, but the power dissipation of the circuit is 50 MW and provides different responses with different temperature.…”

Section: Literature Surveymentioning

confidence: 99%

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

Asharani*,

Chinnaaiah,

Keerthi

et al. 2020

IJITEE

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This paper illustrates the design of low power and high-speed operational Amplifier using Nanoscale Transistors. The proposed design introduces biasing block, for generating I=10uA for Channel length=180nm Technology. Adding biasing block to two-stages operational Amplifier current is constant i.e. there are no fluctuations in power supply, increase in bandwidth and power dissipation is less as compared the previous result. The design is simulated in p-spice tool and performed AC analysis. After analysis, the design achieved the parameter like Gain = 40db, Phase Margin=90º, Unity Gain Band Width=13MHz, Output Swing=0.1v to 1.7v and Power Dissipation=0.145mW.

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“…This is especially true when large output voltage swings are required. For example in [17], a 1.26 V peak-to-peak output swing is achieved with a 1.5 V supply. www.ietdl.org…”

Section: Topologiesmentioning

confidence: 99%

“…The single-ended gain, A (single-ended) , provided by the auxiliary amplifier, from points 1 to 2 is equal to (g m5 R out1 ), where R out1 is shown in (15). This results in the total gain shown in (16) and the unity-gain frequency shown in (17), where R cs is the equivalent resistance of the current source I SS2 of Fig. 4d.…”

Section: Topologiesmentioning

confidence: 99%

“…This is especially true when large output voltage swings are required. For example in [17], a 1.26 V peak‐to‐peak output swing is achieved with a 1.5 V supply.

A_{false(Two - stage false)} = A 1^{*} A 2 = false[g_{m 2} false(r_{normalo 2} / / r_{normalo 4} false) false] false[g_{m 6} false(r_{normalo 6} / / r_{normalo 8} false) false]

f t_{false(Two - stage false)} = \frac{g_{m 1}}{2 π c_{c}}

One of the major drawbacks of using the two‐stage op‐amp is the need for the compensation circuitry to achieve stability.…”

Section: Op‐amp Designmentioning

confidence: 99%

See 1 more Smart Citation

Methodology for designing and verifying switched‐capacitor sample and hold circuits used in data converters

Mohammed¹,

Kawar²,

Abugharbieh³

2014

IET Circuits, Devices & Systems

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This study presents a full methodological approach to designing and verifying differential sample and hold switchedcapacitor circuits generally used in analogue-to-digital converters (ADCs). It provides a step-by-step process for translating system requirements such as signal-to-noise ratio and sampling frequency into ADC requirements and subsequently into operational amplifier topology and specifications. It also includes the design process of a switched-capacitor common mode feedback circuit to control the common mode output voltage. Furthermore, this study discusses the noise aspects of the switched-capacitor circuits. It also provides practical methods for verifying the stability of the system by using step voltage and step current techniques. A design and simulation example for a differential sample and hold switched-capacitor circuit operating in a system requiring a 5 MHz sampling frequency and a 6-bit ADC is provided. Mentor Graphics CAD tools were used in the design and the simulations process by using 180 nm complementary metal oxide semiconductors (CMOS) device models. This study can be used as a resource for the design engineers in the industry as well as the universities teaching graduate level advanced electronics and data converter courses.

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A 1.5 v High Swing Ultra-Low-Power Two Stage CMOS OP-AMP in 0.18 µm Technology

Cited by 12 publications

References 9 publications

Design of a power efficient, high slew rate and gain boosted improved recycling folded cascode amplifier with adaptive biasing technique

Design of a power efficient, high slew rate and gain boosted improved recycling folded cascode amplifier with adaptive biasing technique

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

Methodology for designing and verifying switched‐capacitor sample and hold circuits used in data converters

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