ESSCIRC 80: 6th European Solid State Circuits Conference 1980
DOI: 10.1109/esscirc.1980.5468761
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A 1.5 V, Single-Supply, One-Transistor CMOS EEPROM

Abstract: A 1.5 V, single-supply, one-transistor p-ch CMOS EEPROM array has been de¬ veloped. Negative write and erase voltages of -28V are generated on-chip by voltage multipliers and fed by a 1.5 V logic to the matrix array. Erase and writing times are 25 ms. Endurance is 104 -105 cycles.

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Cited by 3 publications
(4 citation statements)
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“…The simulation results are in good agreement with the theoretical results of (7) and (8). The worst error was lower than 10% and 17% for the double and triple charge pumps respectively and was found after 5 clock periods and for K = 20.…”
Section: Model Validationsupporting
confidence: 83%
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“…The simulation results are in good agreement with the theoretical results of (7) and (8). The worst error was lower than 10% and 17% for the double and triple charge pumps respectively and was found after 5 clock periods and for K = 20.…”
Section: Model Validationsupporting
confidence: 83%
“…The output voltage increment was measured after 5, 10 and 15 clock periods and then compared with the results from (7) or (8). Naturally, to simplify the comparison and for the reason discussed above, we normalized the results to the maximum voltage increment.…”
Section: Model Validationmentioning
confidence: 99%
“…for an even number of stages for an odd number of stages (5) the total charge consumed during the period j can be written as…”
Section: A Behavioral Modelmentioning
confidence: 99%
“…These circuits find applications in power IC's [1]- [4] and EEPROMs [5]- [8]. With the reduction of the power supply to values as low as 1.5 V which allow IC power dissipation to be reduced, the interest in charge pump circuits is continuously growing [9]- [12].…”
Section: Introductionmentioning
confidence: 99%