A simple model describing the dc behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p-and nchannel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (

It is shown that assuming weak inversion, low drain current asymptotic value of the gate equivalent noise resistor is given by n2/2 UT/ID, corresponding to shot noise. Measurements confirming this theory as well as flicker noise measurements on n and p channel transistors integrated with either bulk or SOS CMOS silicon gate technology are presented

A 1.5 V, single-supply, one-transistor p-ch CMOS EEPROM array has been de¬ veloped. Negative write and erase voltages of -28V are generated on-chip by voltage multipliers and fed by a 1.5 V logic to the matrix array. Erase and writing times are 25 ms. Endurance is 104 -105 cycles.

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