A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

Salehi, Mohammad Reza; Dastanian, Rezvan; Abiri, Ebrahim; Nejadhasan, Sajad

doi:10.1016/j.mejo.2015.03.002

Cited by 9 publications

(5 citation statements)

References 12 publications

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“…This circuit includes four parts: the PTAT voltage generator, CTAT voltage generator, weight combination circuit, and bias circuit, which is insensitive to voltage variations. The circuit works as follows: the voltage combination block combines the PTAT voltage (it has a proportional relationship to the absolute temperature) and the CTAT voltage (it has a complementary relationship to the absolute temperature) and produces voltage independent of the temperature [13]. The different parts of the BGR are evaluated in the following sections.…”

Section: Basic Principle Of a Bgrmentioning

confidence: 99%

“…The main core of the PTAT generator includes two NMOS transistors, which are connected to each other, and the output of the PTAT generator is the difference of the gate-source voltages of these two transistors [13,14].…”

Section: Ptat and Ctat Voltage Generatorsmentioning

confidence: 99%

“…where a and b are the weight coefficients of V P T AT and V CT AT , respectively, and are dependent on the capacitance structure of the M a1 and M a2 transistors [13]. That resulted from Eqs.…”

Section: The Weight Combination Circuitmentioning

confidence: 99%

See 2 more Smart Citations

Ultra low-power DC voltage limiter for RFID application in 0.18-$\mu $m CMOS technology

Dastanian¹,

Nejadhasan²

2018

Turk J Elec Eng & Comp Sci

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Section: Basic Principle Of a Bgrmentioning

confidence: 99%

Section: Ptat and Ctat Voltage Generatorsmentioning

confidence: 99%

See 1 more Smart Citation

Ultra low-power DC voltage limiter for RFID application in 0.18-$\mu $m CMOS technology

Dastanian¹,

Nejadhasan²

2018

Turk J Elec Eng & Comp Sci

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“…Voltage references over the past decade have been designed to generate voltage with a temperature coefficient (TC) of almost zero from the sum of the effects of positive and negative temperature coefficient signals using MOS transistors that operate in the weak or strong inversion region. The desire to reduce construction costs also encouraged designers to develop fully MOSFET voltage references [8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

A 2V, 32.13nA, fully MOSFET Voltage Limiter for Low Power Applications

Rayat¹,

Dastanian²

2022

RADIOENGINEERING

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This paper presents a fully MOSFET DC voltage limiter with low current consumption. In the proposed voltage reference structure to reduce power consumption, transistors are biased in the sub-threshold region. To generate complementary to absolute temperature (CTAT) voltage in the voltage reference circuit, only a PMOS transistor is used, in which its drain, gate, and source terminals are connected together and acts as a diode that reduces the layout area occupation. To further reduce power consumption, a part of the rectifier output voltage is compared with the reference voltage by the sampling circuit. Also, four stage inverters are used as buffers to provide the I-V limiting characteristic closer to the ideal situation. The use of series pass-gate transistors in the first inverter also reduces power consumption as much as possible.The results of post-layout simulation based on 0.18μm CMOS technology depict that the suggested voltage reference circuit has a reference voltage equivalent to 0.579 V with a TC of 37.2 ppm/°C in the temperature range of -50°C to 50°C. LR and PSRR attained 0.008%/V and 45 dB, respectively. The output voltage and current consumption of the limiter circuit are 2 V and 32.13 nA, respectively. The total layout area of the proposed limiter is 3249 μm 2 .

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“…In order to produce constant current, proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) techniques, and a combination of them, can be used. [12][13][14] These signals have positive and negative linear relationships with temperature and voltage changes, respectively, and so a constant current can be achieved by merging these signals. However, using this technique in the presence of process variation can cause a complications.…”

Section: Introductionmentioning

confidence: 99%

PVT ‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

Nejadhasan

Zaheri

Abiri

et al. 2020

Int J RF Microw Comput Aided Eng

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In this paper, a low-noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with g m boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.

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A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

Cited by 9 publications

References 12 publications

Ultra low-power DC voltage limiter for RFID application in 0.18-$\mu $m CMOS technology

Ultra low-power DC voltage limiter for RFID application in 0.18-$\mu $m CMOS technology

A 2V, 32.13nA, fully MOSFET Voltage Limiter for Low Power Applications

PVT ‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

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