2013
DOI: 10.1109/tcsi.2012.2215779
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A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection

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Cited by 30 publications
(14 citation statements)
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“…The power consumption of the receiver is 16 mW. The performance reported for similar chips in references [4][5][6] does not include the power consumption of the transmitter. If the power consumption of the transmitter is included, the total power consumption of the references will be much higher than that of this research.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…The power consumption of the receiver is 16 mW. The performance reported for similar chips in references [4][5][6] does not include the power consumption of the transmitter. If the power consumption of the transmitter is included, the total power consumption of the references will be much higher than that of this research.…”
Section: Resultsmentioning
confidence: 99%
“…The MIPI-DigRF M-PHY should be operated in 3 symbol interval (SI) training time which is very short compared with other interfaces such as display port [4][5][6][7]. The length of the SYNC pattern is 3 SI (= 30 UI (unit intervals)), which is 0.01 μs in HS-G2B mode.…”
Section: Introductionmentioning
confidence: 99%
“…State-machine-based FDs can also greatly increase the capture range, but the maximum data rate of this type of FDs is limited by the delay and setup time of digital components [6], [7]. Some unique frequency detection methods take advantage of the 8B/10B encoding data and find their application in certain specialized communication channels [8], [9]. A sophisticated architecture was proposed in [10] to enhance the capture range of a CDR using a delay-locked loop (DLL) for frequency acquisition.…”
Section: Introductionmentioning
confidence: 99%
“…The referenceless CDR satisfies this requirement. The referenceless CDR [3][4][5][6][7][8][9][10][11][12][13][14][15][16] extracts the clock signal from the received data signal alone without using any reference clock sources ( Fig. 1(b)).…”
Section: Introductionmentioning
confidence: 99%
“…One solution to this problem is to limit the output frequency of the voltage-controlled oscillator (VCO) in the referenceless CDR to within ± 50 % of the target frequency [3][4][5][6][7]. However, this restriction limits the usable range of input data rate to a narrow range.…”
Section: Introductionmentioning
confidence: 99%