A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.5dB DR in 20kHz BW

Gönen, Burak; Foti, Sebastiano; Veldhoven, Robert van; Makinwa, Kofi A. A.

doi:10.1109/isscc.2016.7418017

Cited by 25 publications

(8 citation statements)

References 5 publications

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“…This measured PSD profile returns 94.6 dB SNDR in 50-kHz bandwidth and 103.5 dB SFDR. As it can be noticed, no residual flicker noise is observed at low frequency, and no out-band harmonics [9], [10] are present. Fig.…”

Section: Resultsmentioning

confidence: 76%

“…Also, the presented 1/f noise cancellation does not cause the typical ripple and harmonics of chopping solutions [3], [4], [10]. Unlike Zoom ∆ΣMs [9], [10], this modulator does not generate excess of harmonics, and its spectral purity features > 103 dB SFDR up to -1 dBFS input levels.…”

Section: Introductionmentioning

confidence: 94%

“…The required CMFB is realized through the passive capacitive divider (C cmfb ) and the control (M13n-M15n) of the NMOS differential pair current tail. Compared to the use of pseudo-differential inverterbased OpAmps [9], fully differential topologies should achieve higher PSRR and CMRR figures. Finally, the Class-AB operation driven by these variable mirrors relay on device matching only, which explains the low sensitivity to process and temperature corners of Fig.…”

Section: Low-power Cmos Switched Opampsmentioning

confidence: 99%

“…In the above design scenario, several ∆ΣM architectural strategies are employed in order to improve dynamic range: high-order (≥ 4) single-loop noise shaping [2], [3], [6], [7], which is prone to instability; multi-stage noise shaping (MASH) [4], [8] that tends to suffer from technology mismatching at the reconstruction filtering; and SAR-driven Zoom ∆ΣMs [9], [10], whose internal full-scale control introduces glitches and excess of out-of-band harmonics. At CMOS circuit level, flicker noise contributions in the kHz range are commonly attenuated in fully differential topologies by the use of chopping [3], [4], [10] despite the resulting ripple and harmonics.…”

Section: Introductionmentioning

confidence: 99%

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A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation

Suanes

Terés

Dei

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a 0.8-mW 0.2-mm 2 9-level second-order single-loop SC Delta-Sigma modulator (ΔΣM) ADC in 1.8-V 0.18-μm CMOS technology for low-power high-resolution sensing applications. The ΔΣM circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dB FS input for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOM S . The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10-μW resistor-less flash quantizer. The obtained 172.6-dB FOM S is competitive within the state-of-art high-resolution (SNDR > 90 dB) and generalpurpose (bandwidth > 20 kHz) SC ΔΣM ADCs.

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Section: Resultsmentioning

confidence: 76%

Section: Introductionmentioning

confidence: 94%

Section: Low-power Cmos Switched Opampsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation

Suanes

Terés

Dei

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…16 shows the SNDR over the input signal in-band frequency for the triple-mode. Due to the increase of the noise floor in the out-of-band mentioned by other reported zoom ADCs [28] and the insufficient settling time of the IADC, the SNDR of a high and medium-resolution mode are decreased at frequencies above about 6 kHz. However, the low-power mode has a much wider bandwidth than the other modes because it is operated by the SAR-EC structure with a relatively small integrator capacitor and T-network, which reduces the settling time required for stable operation.…”

Section: Measurement Resultsmentioning

confidence: 95%

A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications

Park

Kim

2019

IEEE Access

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This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution and power consumption in various smart sensor applications. It mainly consists of an incremental delta-sigma modulator and the proposed SAR-EC sub-ADC for alternate operation of the coarse SAR conversion and EC. They can be reconfigured to operate separately depending on the application requirements. The SAR-based zooming structure allows the IADC to have better linearity and resolution, and additional activation of the EC function gives the further resolution. During this reconfigurable conversion process, pipelined reusing operation of sub-blocks reduces the silicon area and the number of cycles for target resolutions. A prototype ADC is fabricated in a 180-nm CMOS process, and its triple-mode operation of high-resolution, medium-resolution, and lowpower is experimentally verified to achieve 116.1-, 109.4-, and 73.3-dB dynamic ranges, consuming 1.60, 1.26, and 0.39 mW, respectively. INDEX TERMS Analog-to-digital converter (ADC), incremental ADC, triple-mode, SAR-based zooming, extended counting, pipeline operation.

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Time-Discrete Σ Δ Modulation

Pelgrom

2021

Analog-to-Digital Conversion

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A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.5dB DR in 20kHz BW

Cited by 25 publications

References 5 publications

A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation

A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation

A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications

Time-Discrete Σ Δ Modulation

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