This paper presents a dynamic zoom ADC. Intended for audio applications, it achieves 109 dB DR, 106 dB SNR, and 103 dB SNDR in a 20kHz bandwidth, while dissipating only 1.12mW. This translates into state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves state-of-the-art area efficiency, occupying only 0.16mm 2 in 0.16-μm CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques and a dynamically biased inverter-based OTA.

This paper presents a continuous-time (CT) zoom ADC for use in audio applications. Compared to previous zoom ADCs, its input impedance is mainly resistive, making it much easier to drive while still maintaining high energy efficiency. The prototype is fabricated in a 0.16 pm CMOS process, occupies 0.27 mm2 and achieves 108.5 dB DR, 108.1 dB SNR, 106.4 dB SNDR in a 20 kHz BW, while consuming 618 pW. This results in a state-of-the-art Schreier FoM of 183.6 dB.

This paper presents a high-resolution 110dB SNR ΔΣ ADC that achieves a ±30V input common-mode voltage range (CMVR) while powered from a single 5V supply. This beyond-the-rails capability is obtained by employing a capacitively coupled high-voltage (HV) chopper at the input of a switched-capacitor (SC) ΔΣ ADC. Furthermore, the use of correlated double sampling and system-level chopping results in a maximum offset of 8μV over the full CMVR. In contrast to a recent HV ADC [1], the ADC exhibits 30dB more resolution, while its CMVR extends below the negative rail.The ADC is intended for current monitoring applications, in which a small voltage drop across a shunt resistor must be digitized. In battery monitoring applications, or when inductive loads are involved, the differential voltage across the shunt will often be accompanied by beyond-the-rails common-mode (CM) voltages. Conventionally, current monitoring systems consist of a precision current sensing amplifier (CSA) with a wide CMVR, whose output is then digitized by an ADC [2]. The CSA thus isolates the ADC from large CM voltages, while its gain relaxes the ADC noise requirements. Since the presented ADC itself has beyond-the-rails CM capability together with high resolution, low offset and high gain accuracy, it obviates the need for the CSA, thus reducing the power consumption and the silicon area of the resulting current monitoring system. Figure 5.2.1 shows the block diagram of the ADC. It consists of a single-loop single-bit 3 rd -order SC ΔΣ ADC with a feed-forward architecture based on three OTAs and a SC summing network. An inner set of HV choppers, CH in , together with switches Φ1 and Φ2, implement a correlated double sampling (CDS) scheme that mitigates the effect of offset and 1/f noise of the 1 st OTA. Further offset reduction is obtained with the help of an outer set of HV choppers, CH sys , which, together with a digital chopper at the output of the modulator, implement a system-level chopping scheme. During Φ1, the input signal, V in , and the OTA offset are sampled on the 5pF input capacitors, C s . During Φ2, the HV chopper, CH in , reverses the input and thus transfers a charge packet proportional to 2•C s •V in to the integration capacitors, C int . This cross-coupled sampling scheme [3] ensures that the only components exposed to the input CM voltage are the capacitors C s and two capacitively coupled HV choppers. The input capacitors are implemented as HV fringe capacitors with a breakdown voltage of 80V. The feedback capacitors are also implemented with the same type of capacitors, to ensure good matching and hence, good gain accuracy.Figure 5.2.2 shows the schematic of the capacitively-coupled HV chopper, which consists of 4 sampling switches MN 1-4 , one dynamic latch MN 5,6 , three coupling capacitors C 1-3 and a minimum selector MN S1-2 . All the transistors are 5V NMOS devices located in an isolated HV N-Epi pocket (Fig. 5.2.2). The N-Epi pocket is capable of floating up to 65V with regard to the grounded P-Substrate, while the local...

This paper presents a continuous-time zoom ADC for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuoustime delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160 nm CMOS process, the ADC occupies 0.27 mm 2 and achieves 108.1 dB peak SNR, 106.4 dB peak SNDR and 108.5 dB dynamic range in a 20 kHz bandwidth, while consuming 618 μW. This results in a Schreier FoM of 183.6 dB. Index Terms-A/D conversion, audio ADC, delta-sigma ADC, asynchronous SAR ADC, inverter-based OTA, low power circuits, dynamic zoom ADC, continuous-time delta-sigma.

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