This paper presents a high-resolution 110dB SNR ΔΣ ADC that achieves a ±30V input common-mode voltage range (CMVR) while powered from a single 5V supply. This beyond-the-rails capability is obtained by employing a capacitively coupled high-voltage (HV) chopper at the input of a switched-capacitor (SC) ΔΣ ADC. Furthermore, the use of correlated double sampling and system-level chopping results in a maximum offset of 8μV over the full CMVR. In contrast to a recent HV ADC [1], the ADC exhibits 30dB more resolution, while its CMVR extends below the negative rail.The ADC is intended for current monitoring applications, in which a small voltage drop across a shunt resistor must be digitized. In battery monitoring applications, or when inductive loads are involved, the differential voltage across the shunt will often be accompanied by beyond-the-rails common-mode (CM) voltages. Conventionally, current monitoring systems consist of a precision current sensing amplifier (CSA) with a wide CMVR, whose output is then digitized by an ADC [2]. The CSA thus isolates the ADC from large CM voltages, while its gain relaxes the ADC noise requirements. Since the presented ADC itself has beyond-the-rails CM capability together with high resolution, low offset and high gain accuracy, it obviates the need for the CSA, thus reducing the power consumption and the silicon area of the resulting current monitoring system. Figure 5.2.1 shows the block diagram of the ADC. It consists of a single-loop single-bit 3 rd -order SC ΔΣ ADC with a feed-forward architecture based on three OTAs and a SC summing network. An inner set of HV choppers, CH in , together with switches Φ1 and Φ2, implement a correlated double sampling (CDS) scheme that mitigates the effect of offset and 1/f noise of the 1 st OTA. Further offset reduction is obtained with the help of an outer set of HV choppers, CH sys , which, together with a digital chopper at the output of the modulator, implement a system-level chopping scheme. During Φ1, the input signal, V in , and the OTA offset are sampled on the 5pF input capacitors, C s . During Φ2, the HV chopper, CH in , reverses the input and thus transfers a charge packet proportional to 2•C s •V in to the integration capacitors, C int . This cross-coupled sampling scheme [3] ensures that the only components exposed to the input CM voltage are the capacitors C s and two capacitively coupled HV choppers. The input capacitors are implemented as HV fringe capacitors with a breakdown voltage of 80V. The feedback capacitors are also implemented with the same type of capacitors, to ensure good matching and hence, good gain accuracy.Figure 5.2.2 shows the schematic of the capacitively-coupled HV chopper, which consists of 4 sampling switches MN 1-4 , one dynamic latch MN 5,6 , three coupling capacitors C 1-3 and a minimum selector MN S1-2 . All the transistors are 5V NMOS devices located in an isolated HV N-Epi pocket (Fig. 5.2.2). The N-Epi pocket is capable of floating up to 65V with regard to the grounded P-Substrate, while the local...

This paper presents the most accurate shunt-based high-side current sensor ever reported. It achieves a 25V input common-mode range from a single 1.8V supply by using a beyond-the-rails ADC. A hybrid analog/digital temperature compensation scheme is proposed to simplify the circuit implementation while maintaining the state-of-the-art accuracy. Over a ±12A current range, the sensor exhibits 0.35% gain error from-40°C to 85°C with 3x better power efficiency.

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This paper presents a fully integrated shunt-based current sensor that supports a 25-V input common-mode range while operating from a single 1.5-V supply. It uses a highvoltage beyond-the-rails ADC to directly digitize the voltage across an on-chip shunt resistor. To compensate for the shunt's large temperature coefficient of resistance (∼0.335%/°C), the ADC employs a proportional-to-absolute-temperature voltage reference. This analog compensation scheme obviates the need for the explicit temperature sensor and calibration logic required by digital compensation schemes. The sensor achieves 1.5-μV rms noise over a 2-ms conversion time while drawing only 10.9 μA from a 1.5-V supply. Over a ±4-A range, and after a one-point trim, the sensor exhibits a 0.9% (maximum) gain error from −40°C to 85°C and a 0.05% gain error at room temperature.

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