A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration

Abstract

A 16x16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The I/O also includes an 8:1 TX serializer with 8-phase clocking, and an active-inductor-based RX CTLE whose outputs form current mirrors with the inputs of the RX samplers. A phase rotator based on currentintegrating phase interpolator cores is described, with architecture and circuit improvements to performance as compared to prior art. 16-Gb/s link measurements over Megtron-6 traces demonstrate efficiencies of 1.8pJ/bit (0.75" traces) and 1.9pJ/bit (10" traces) with >30% timing margin, with the TX, RX, and PLL operating from 1V supplies.

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“…The signalling topology uses passive termination on the transmitter for equalization. Dickson et al showed source synchronous parallel links for chip to chip communication [20][21] [22]. For equalization at the receiver, decision feedback equalization (DFE) was implemented with infinite impulse response (IIR) along with standard digital DFE.…”

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“…To overcome the metastability problem, we can also implement a source synchronous interface [7], where the sending node sends its clock signal through a clock path to the receiving node. The sent clock signal is certainly used to synchronized the transmitted data.…”