A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

Abstract

A set of low-power techniques is proposed to realize low power design in pipeline analog-to-digital converter (ADC). These techniques include removing the active S/H (i.e., SHA-less), sharing the opamp between the adjacent multi-bit-per-stages, low-power high-efficiency high-swing amplifier technique. Also, a new sampling topology is proposed to minimize aperture error by matching the time constant between the two input signal paths. All these skills are verified by simulation in the design of the 1.8-V 11-bit 40-MHz ADC in a 0.18-lm CMOS process with power dissipation 21-mW, signal-tonoise-and-distortion ratio (SNDR) 65-dB, effective number of bit (ENOB) 10.5-bit, spurious free dynamic range (SFDR) 78-dB, total harmonic distortion (THD) -75.4-dB, signal-to-noise ratio (SNR) 65.4-dB and figure-of-merit (FOM) 0.18 pJ/step.

An ultra low die area 8-b ADC and its generic calibration logic

“…Pipeline or subrange [11][12][13][14] and folding/interpolating [15][16][17] architectures are often used for such applications since they require lower area and power than the flash ones while at the same time they can achieve remarkably high conversion rates.…”