A new tri-level switching method for successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. The proposed switching method enhances the efficiency of digital-to-analogue converter switching energy by 93.7% and achieves a 75% reduction in the total capacitor size, compared with the conventional SAR ADC. In addition, the accuracy of the proposed SAR ADC has no dependency on the accuracy of the mid-level reference voltage (V cm) except in the least significant bit, and the common-mode voltage at the input of the comparator will remain approximately unchanged. Analytical calculations and behavioural simulation results are provided to demonstrate the effectiveness of the proposed switching scheme.

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This paper presents the analysis of hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensation methods, which is used in two-stage CMOS operational transconductance amplifiers (OTAs). The open loop signal transfer function is derived to allow the accurate estimation of the poles and zeros. This analytical approach shows that the non-dominant poles and zeros of the hybrid cascode compensation are about 40 percent greater than those of the conventional cascode compensation. Circuit level simulation results are provided to show the accuracy of the calculated expressions and also the usefulness of the proposed cascode compensation technique.

SUMMARYEmbedding the time encoding approach inside the loop of the sigma-delta modulators has been shown as a promising alternative to overcome the resolution problems of analog-to-digital converters in low-voltage complementary metal-oxide semiconductor (CMOS) circuits. In this paper, a wideband noise-transferfunction (NTF)-enhanced time-based continuous-time sigma-delta modulator (TCSDM) with a secondorder noise-coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage-to-time converter and a time-to-digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog-based noise-coupling technique, the modulator's noise-shaping order is improved by two. The concept is elaborated for an NTF-enhanced second-order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit-level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time-based noise-coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced.

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