SUMMARYEmbedding the time encoding approach inside the loop of the sigma-delta modulators has been shown as a promising alternative to overcome the resolution problems of analog-to-digital converters in low-voltage complementary metal-oxide semiconductor (CMOS) circuits. In this paper, a wideband noise-transferfunction (NTF)-enhanced time-based continuous-time sigma-delta modulator (TCSDM) with a secondorder noise-coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage-to-time converter and a time-to-digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog-based noise-coupling technique, the modulator's noise-shaping order is improved by two. The concept is elaborated for an NTF-enhanced second-order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit-level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time-based noise-coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced.

Summary In this paper, a new type of an oscillatory noise‐shaped quantizer (NSQ) for time‐based continuous‐time sigma‐delta modulators is presented. The proposed NSQ is composed of an oscillatory voltage‐to‐time converter and a polyphase sampler. Using Tustin's transformation method and through the approximation of the comparator gain, a linearized model of the NSQ is introduced. This way, a novel realization of the first‐ and second‐order NSQ is presented. Its implementation is based on fully passive continuous‐time filters without needing any amplifier or power consuming element. The ploy‐phase sampler inside the NSQ is based on the combination of a time‐to‐digital and a digital‐to‐time converter. The layout of the proposed NSQ is provided in Taiwan Semiconductor Manufacturing Company 0.18 μm complementary metal‐oxide‐semiconductor 1P6M technology. The verification of the proposed NSQ is done via investigating both the system level and postlayout simulation results. Leveraging the proposed NSQ in an Lth‐order time‐based continuous‐time sigma‐delta modulator enhances the noise‐shaping order up to L + 2, confirming its superior effectiveness. This makes it possible to design high performance and wideband continuous‐time SDMs with low power consumption and relaxed design complexity.

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A high resolution highly linear low spur fractional time-todigital converter (FTDC) for All Digital PLL (ADPLL) is presented. This FTDC employs a linear high gain time amplifier (TAMP) and a spur reduction digital filter to eliminate the spurs at the output. Unlike conventional TDCs, no delay line is utilized in the new FTDC, and hence no mismatch error cancelation technique is required. The FTDC structure is verified in theory and via simulation using an 180 nm CMOS technology. The results illustrate a time resolution of 5 psec, differential nonlinearity (DNL) free dynamic range of about 350 psec, and the total power consumption, apart from the clock generator, of nearly 3 mW.

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