A 1.8 V 36 mW DSP for the half-rate speech codec

Shiraishi, Taketora; Kawamoto, Koji; Ishikawa, Kazuhiko; Sato, H.; Asai, F.; Teraoka, E.; Kengaku, T.; Takata, Hitoshi; Tokuda, T.; Nishida, Katsumi; Saitoh, Kazunori

doi:10.1109/cicc.1996.510578

Cited by 8 publications

(1 citation statement)

References 2 publications

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“…Since one frame is composed of 240 samples with the sampling rate of 8kHz, the whole codec process per frame has to be completed within 30 msec so that a decoding speech signal should not be broken. Consequently, in order to realize a realtime codec with the use of this conventional 16 bit DSP, a clock frequency needs 49.66MHz in case of ( 10). Mechanism A improves the processing ability, but increases the chip size because of the added pipeline registers.…”

Section: A Computational Cost Analysismentioning

confidence: 99%

Implementation of H.324 audiovisual codec for mobile computing

Fujita

Okuhata²,

Miki³

et al.

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143)

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Phone: +81(6)879-7808, Fax: +81(6)875-5902, Email: {fujita, okuhata, miki, onoe, sirakawa} Bise.eng.osaka-u.ac.jp Dec.Abstract A VLSI implementation of the H.324 audiovisual codec is described. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The proposed audiovisual codec core has been implemented by using 0.35pm CMOS 4LM technology, which contains totally 420k transistors with the dissipation of 224.32mW from single 3.3V supply. IntroductionThe H.324(1) international standard specifies the low bitrate audiovisual communication based on PSTN (Pub-

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Section: A Computational Cost Analysismentioning

confidence: 99%