Low-power implementation of H.324 audiovisual codec dedicated to mobile computing

Onoye, Takao; Fujita, Gen; Okuhata, Hiroyuki; Miki, Morgan Hirosuke; Shirakawa, Isao

doi:10.1109/aspdac.1998.669566

Cited by 1 publication

(2 citation statements)

References 16 publications

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“…Only in [14] it is possible to scale the architecture for better performance by adding modular processors to the system. All of the referred encoders utilize hardware accelerators to implement the entire encoder [13] or for the computation intensive operations [12,[14][15][16].…”

Section: Shared Memory Approachmentioning

confidence: 99%

“…For portable devices, programmability is often sacrificed for other design requirements. Most of those architectures rely on dedicated processing elements that give the highest processing efficiency with respect to the hardware usage and power consumption [12][13][14][15][16][17]. As a drawback, dedicated architectures are non-flexible as they are adapted to the processing of a specific algorithm.…”

Section: Introductionmentioning

confidence: 99%

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Scalable Architecture for SoC Video Encoders

Kangas

Hämäläinen

Kuusilinna

2006

J VLSI Sign Process Syst Sign Image Video Technol

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Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers.

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