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This paper analyses the performance of IEEE 802.15.4 Low-Rate Wireless Personal Area Network (LR-WPAN) in a large-scale Wireless Sensor Network (WSN) application. To minimize the energy consumption of the entire network and to allow adequate network coverage, IEEE 802.15.4 peer-to-peer topology is selected, and configured to a beacon-enabled cluster-tree structure. The analysis consists of models for CSMA-CA mechanism and MAC operations specified by IEEE 802.15.4. Network layer operations in a cluster-tree network specified by ZigBee are included in the analysis. For realistic results, power consumption measurements on an IEEE 802.15.4 evaluation board are also included. The performances of a device and a coordinator are analyzed in terms of power consumption and goodput. The results are verified with simulations using WIreless SEnsor NEtwork Simulator (WISENES). The results depict that the minimum device power consumption is as low as 73 µW, when beacon interval is 3.93 s, and data are transmitted at 4 min intervals. Coordinator power consumption and goodput with 15.36 ms CAP duration and 3.93 s beacon interval are around 370 µW and 34 bits/s.

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This paper describes a complete design flow for multiprocessor systems-on-chips (SoCs) covering the design phases from system-level modeling to FPGA prototyping. The design of complex heterogeneous systems is enabled by raising the abstraction level and providing several system-level design automation tools. The system is modeled in a UML design environment following a new UML profile that specifies the practices for orthogonal application and architecture modeling. The design flow tools are governed in a single framework that combines the subtools into a seamless flow and visualizes the design process. Novel features also include an automated architecture exploration based on the system models in UML, as well as the automatic back and forward annotation of information in the design flow. The architecture exploration is based on the global optimization of systems that are composed of subsystems, which are then locally optimized for their particular purposes. As a result, the design flow produces an optimized component allocation, task mapping, and scheduling for the described application. In addition, it implements the entire system for FPGA prototyping board. As a case study, the design flow is utilized in the integration of state-of-the-art technology approaches, including a wireless terminal architecture, a network-on-chip, and multiprocessing utilizing RTOS in a SoC. In this study, a central part of a WLAN terminal is modeled, verified, optimized, and prototyped with the presented framework.