Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core

Hämäläinen, Päivi; Alho, Timo; Hännikäinen, Marko; Hämäläinen, Timo D.

doi:10.1109/dsd.2006.40

Cited by 231 publications

(148 citation statements)

References 8 publications

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“…The third and fourth rows are shifted left by two and three positions, correspondingly. [7] [8] [9].…”

Section: Shift Row Layermentioning

confidence: 99%

S-Box Design Analysis and Parameter Variation in AES Algorithm

Kohli¹,

Sharma²,

Baliyan³

2012

IJCA

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In this paper fundamental scrutiny of AES algorithm with the non serviceable aspects i.e. elevated performance, high throughput, and area efficiency is offered. A virtual analysis of DES, 3DES and AES is shown. This paper will present the theoretical analysis of parameter variations in the generation of the S-BOX. The Rijndael cipher, premeditated by Joan Daemen and Vincent Rijmen, is particular as authorized Advance Encryption standard (AES) and it is well apt for hardware exercise.

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“…The third and fourth rows are shifted left by two and three positions, correspondingly. [7] [8] [9].…”

Section: Shift Row Layermentioning

confidence: 99%

S-Box Design Analysis and Parameter Variation in AES Algorithm

Kohli¹,

Sharma²,

Baliyan³

2012

IJCA

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“…A lightweight AES core requiring 3400 GE and more than 1000 clock cycles has been first published in [7]. A different implementation of the AES requires only 3100 GE and is more than six times faster than the previous one [9]. In [14] a different approach is followed: DES and DESX have been slightly modified to DESL/DESXL and yield a more compact implementation without scrutinizing the security.…”

Section: Previous Workmentioning

confidence: 99%

256 Bit Standardized Crypto for 650 GE – GOST Revisited

Pöschmann

Ling

Wang

2010

Cryptographic Hardware and Embedded Systems, CHES 2010

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Abstract. The former Soviet encryption algorithm GOST 28147-89 has been standardized by the Russian standardization agency in 1989 and extensive security analysis has been done since. So far no weaknesses have been found and GOST is currently under discussion for ISO standardization. Contrary to the cryptographic properties, there has not been much interest in the implementation properties of GOST, though its Feistel structure and the operations of its round function are well-suited for hardware implementations. Our post-synthesis figures for an ASIC implementation of GOST with a key-length of 256 bits require only 800 GE, which makes this implementation well suitable for low-cost passive RFID-tags. As a further optimization, using one carefully selected S-box instead of 8 different ones -which is still fully compliant with the standard specifications!-the area requirement can be reduced to 651 GE.

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“…There is only a single block for both P and Q operations in order to save area, which also allows us to use the same block for both the f and the output transformation functions. The design basically implements a modified version of the serial AES-like data flow in [23]. While the message is processed in P mode, it is also stored inside a temporary register.…”

Section: A Message Authenticationmentioning

confidence: 99%

IPSecco: A lightweight and reconfigurable IPSec core

Driessen

Güneysu

Mischke

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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Abstract-In this paper we propose a reconfigurable lightweight Internet Protocol Security (IPSec) hardware core. Our architecture supports the main IPSec protocols; namely Authentication Header (AH), Encapsulating Security Payload (ESP), and Internet Key Exchange (IKE). In this work, the cryptographic algorithms and their modes of operation, which are at the heart of the IPSec protocols, are implemented in hardware. Instead of re-implementing common IPSec configurations, which are deemed "too heavy" for pervasive devices, we evaluate efficient implementations of standardized and/or well-known lightweight and hardware-friendly algorithms. In particular, we examine different versions of PRESENT, GRØSTL, PHOTON, and a very compact ECC core. As a consequence, we present IPSECCO, a core with adequate security and only moderate resource requirements, making it suitable for lightweight devices. We selected the Xilinx Spartan family of Field Programmable Gate Arrays (FPGA) as target platform due its low-power footprint and reduced costs compared to other FPGAs. Our results show that it is possible to realize a high performance IPSec core even on members of the Spartan-3 family.

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Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core

Cited by 231 publications

References 8 publications

S-Box Design Analysis and Parameter Variation in AES Algorithm

S-Box Design Analysis and Parameter Variation in AES Algorithm

256 Bit Standardized Crypto for 650 GE – GOST Revisited

IPSecco: A lightweight and reconfigurable IPSec core

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