A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS

Uyttenhove, K.; Steyaert, Michiel

doi:10.1109/jssc.2003.813244

Cited by 142 publications

(42 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For this, an analog to digital converter (ADC) and time to digital converter (TDC) [14] based on a common time based ADC (TAD) architecture has been investigated. It is concluded that the proposed fully digital time-based ADC architecture can also be operated as TDC.…”

Section: Vineet Sharma Etalmentioning

confidence: 99%

A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology

Kakaria¹,

Tiwari²

2017

IJCA

View full text Add to dashboard Cite

This work describes a 12-bit pipeline ADC (Analog-toDigital Converter) for CMOS (Complementary Metal Oxide Semiconductor) that is implemented in a TSMC 0.18μm CMOS process. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded CMOS inverters as a comparator. the TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other ADCs The sample and hold circuit have high Sampling rate. This Design is implemented and Fabricated in TSMC 0.18μm CMOS verified on the LT SPICE in 0.18µm Technology.

show abstract

Section: Vineet Sharma Etalmentioning

confidence: 99%

A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology

Kakaria¹,

Tiwari²

2017

IJCA

View full text Add to dashboard Cite

show abstract

“…The DDA as illustrated in Fig. 4 has been used as the first-stage pre-amp of a highspeed comparator since it operates at high speed without the glitch noise and gain reduction due to sampling switches and capacitors [10,12]. At the output of the DDA, passive resistors or diode-connected MOS transistors are usually employed to obtain the required DC gain and bias voltage.…”

Section: High-speed Comparator With a Wide Input Rangementioning

confidence: 99%

A 6b 1.2 GS/s 47.8 mW 0.17 mm²65 nm CMOS ADC for High-Rate WPAN Systems

Park¹,

Kwon²,

Choi³

et al. 2011

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

“…Recently several high-speed, high-resolution CMOS pipelined A/D converters with the operational frequency up to MHz have been reported [4], [5]. ADCs are widely used in many applications including data storage systems, fast serial links and high-speed measurement instruments.…”

Section: Introductionmentioning

confidence: 99%

High Speed and High Resolution Self Biased Differential Amplifier based Latch Comparator

Singh¹,

Kumar²,

Paraliya³

2013

IJCA

View full text Add to dashboard Cite

In high speed ADC, comparator influences the overall performance of ADC directly. This paper describes a very high speed and high resolution preamplifier comparator. The comparator use a self biased differential amp to increase the output current sinking and sourcing capability. The threshold and width of the new comparator can be reduced to the millivolt (mV) range, the resolution and the dynamic characteristics are good. Based on UMC 0.18um CMOS process model, simulated results show the comparator can work under a 25dB gain, 55MHz speed and 210.10µW power . KeywordsHigh speed ADC, high speed comparator, high resolution and preamplifier latch comparator. .

show abstract

A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS

Cited by 142 publications

References 10 publications

A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology

A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology

A 6b 1.2 GS/s 47.8 mW 0.17 mm²65 nm CMOS ADC for High-Rate WPAN Systems

High Speed and High Resolution Self Biased Differential Amplifier based Latch Comparator

Contact Info

Product

Resources

About

A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS

Cited by 142 publications

References 10 publications

A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology

A Review on Pipe Line Analog to Digital Converter using 0.18µm CMOS Technology

A 6b 1.2 GS/s 47.8 mW 0.17 mm265 nm CMOS ADC for High-Rate WPAN Systems

High Speed and High Resolution Self Biased Differential Amplifier based Latch Comparator

Contact Info

Product

Resources

About

A 6b 1.2 GS/s 47.8 mW 0.17 mm²65 nm CMOS ADC for High-Rate WPAN Systems