A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency

Taft,; Francese, Pier Andrea; Tursi,; Hidri,; Hoehn,; Schmitz,; Werker,; Glenny, Anne‐Marie

doi:10.1109/isscc.2009.4977316

Cited by 14 publications

(10 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Folding significantly reduces the number of comparators, because it divides the high-resolution ADC into coarse and fine ADCs with lower resolutions. Combining interpolation and folding architectures is a popular technique to achieve better power and area efficiency, as in [40,41], for instance. The high power consumption and limited bandwidth of the preamplifiers, nonlinearity of the practical folding circuit, and the delay of the folding path are the main limiting factors in folding and interpolating ADC architectures.…”

Section: Interpolating and Folding Adcsmentioning

confidence: 99%

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

View full text Add to dashboard Cite

This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

show abstract

Section: Interpolating and Folding Adcsmentioning

confidence: 99%

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

View full text Add to dashboard Cite

show abstract

“…So their circuits should be as simple as possible. In published works [5,7,10], CMOS switches are used as inter-stage sampling switches, but for low-voltage applications, the on-resistance is increased due to the lower overdrive voltage of CMOS switches, which introduces a longer signal pre-processing delay. As an alternative, a real bootstrapped switch is useful to lower the on-resistance and reduce this delay in the low supply voltage application.…”

Section: Coarse-stage-free Joint Encodingmentioning

confidence: 99%

“…Folding and interpolating are both methods of reducing the power consumption in the flash-type ADCs [5,6,7,8,9,10,11]. The folding architecture reduces the number of comparators and the interpolating architecture reduces the number of pre-amplifiers.…”

Section: Introductionmentioning

confidence: 99%

“…A power-efficient averaging method is proposed to improve mismatches among folders or interpolators [8,9]. A pipelined folding interpolating architecture is proposed to reach higher sampling rate [7,10]. But the method how to reduce the power consumption is not proposed in previous designs.…”

Section: Introductionmentioning

confidence: 99%

“…Meanwhile, a new double-diode bootstrapped switch based on [13] is proposed to reduce the delay between the adjacent stages. What's more, the linearity of signals limits the supply voltage [7,10], so a rail-to-rail preamplifier is proposed to meet a low voltage supply application.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 7 bit 1 GS/s pipelined folding and interpolating ADC with <i>coarse-stage-free joint encoding</i>

Wang¹,

Ye³

et al. 2014

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a single-channel 1.0-GS/s 7-bit pipelined folding and interpolating analog-to-digital converter (PL-FAI-ADC) used in ultra wide band (UWB) system. An improved joint encoding method is proposed to eliminate the coarse sub-ADC and reduce the power consumption. Double-diode bootstrapped inter-stage switch is adopted to reach the pipelined working and improve the overall efficiency of speed. The ADC implemented in 0.13-µm CMOS technology achieves the signal-to-noise-and-distortion ratio (SNDR) of 37.89 dB and the spurious-free dynamic range (SFDR) of 45.89 dB for 498 MHz input frequency at the rate of 1.0 GS/s. The power consumption is 98 mW with sampling rate of 1.0 GS/s and supply voltage of 1.2/ 2.5 V. The peak figure-of-merit (FoM) is 1.54 pJ/conversion-step.

show abstract

GS/s AD Conversion for Broadband Multi-stream Reception

Janssen

Zanikopoulos

Doris

et al. 2012

Nyquist AD Converters, Sensor Interfaces, and Robustness

View full text Add to dashboard Cite

A 1.8V 1.0GS/s 10b self-calibrating unified-folding-interpolating ADC with 9.1 ENOB at Nyquist frequency

Cited by 14 publications

References 5 publications

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

A 7 bit 1 GS/s pipelined folding and interpolating ADC with <i>coarse-stage-free joint encoding</i>

GS/s AD Conversion for Broadband Multi-stream Reception

Contact Info

Product

Resources

About