A 1.92¿s-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors

Fukuoka, Kazuki; Ozawa, O.; Mori, Ryota; Igarashi, Yasuto; Sasaki, Tadahiro; Kuraishi, Takashi; Yasu, Y.; Ishibashi, Koji

doi:10.1109/vlsic.2007.4342685

Cited by 12 publications

(4 citation statements)

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“…One well-known low-power circuit scheme is an on-chip power-isolation switch (OPS) scheme [2]. This scheme is very effective for reducing leakage when an LSI's function block is in the standby state.…”

Section: Introductionmentioning

confidence: 99%

Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs

Sakimura

Sugibayashi

Nebashi

et al. 2008

2008 IEEE Custom Integrated Circuits Conference

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A nonvolatile Magnetic Flip-Flop (MFF) primitive cell for SoC design libraries has been developed using a unique MRAM process. It has high design compatibility with conventional CMOS LSI designs. MFF maximum frequency was estimated to be 3.5 GHz, which is comparable to that of a normal CMOS DFF. An MFF test chip was fabricated with the process. The chip's functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of SoCs dramatically.

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Section: Introductionmentioning

confidence: 99%

Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs

Sakimura

Sugibayashi

Nebashi

et al. 2008

2008 IEEE Custom Integrated Circuits Conference

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“…For instance, an implementation can include a power savings technique in which the FFT computing module can be operated in "sleep modes", where, the idle times are power gated to the computing module (i.e., the power supply is completely disconnected from the computing module). Guard times would then need to compensate for the wake-up time (i.e., the transition from a sleep mode to a computation mode) in addition to data load and read [74]- [77]. The resulting guard times will typically be on the order of microseconds, i.e., a small fraction of the typical OFDM symbol durations of 40 and 80 µsecs.…”

Section: Interleaving Timing Of Fft Computationsmentioning

confidence: 99%

R-FFT: Function Split at IFFT/FFT in Unified LTE CRAN and Cable Access Network

Thyagaturu

Alharbi

Reisslein

2018

IEEE Trans. on Broadcast.

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The Remote-PHY (R-PHY) modular cable network for Data over Cable Service Interface Specification (DOCSIS) service conducts the physical layer processing for the transmissions over the broadcast cable in a remote node. In contrast, the cloud radio access network (CRAN) for Long-Term Evolution (LTE) cellular wireless services conducts all baseband physical layer processing in a central baseband unit and the remaining physical layer processing steps towards radio frequency (RF) transmission in remote nodes. Both DOCSIS and LTE are based on Orthogonal Frequency Division Multiplexing (OFDM) physical layer processing. We propose to unify cable and wireless cellular access networks by utilizing the hybrid fiber-coax (HFC) cable network infrastructure as fiber fronthaul network for cellular wireless services. For efficient operation of such a unified access network, we propose a novel Remote-FFT (R-FFT) node that conducts the physical layer processing from the Fast-Fourier Transform (FFT) module towards the RF transmission, whereby DOCSIS and LTE share a common FFT module. The frequency domain in-phase and quadrature (I/Q) symbols for both DOCSIS and LTE are transmitted over the fiber between remote node and cable headend, where the remaining physical layer processing is conducted. We further propose to cache repetitive quadrature amplitude modulation (QAM) symbols in the R-FFT node to reduce the fronthaul bitrate requirements and enable statistical multiplexing. We evaluate the fronthaul bitrate reductions achieved by R-FFT node caching, the fronthaul transmission bitrates arising from the unified DOCSIS and LTE service, and illustrate the delay implications of moving part of the cable R-PHY remote node physical layer processing to the headend. Overall, our evaluations indicate that the proposed R-FFT node can effectively support unified DOCSIS and LTE services over the HFC cable plant while substantially reducing the fronthaul bitrate requirements of the existing CRAN structures.

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“…The main reasons are 0 V initial voltage and feedback effect. However, the longer sensing delay, which is a few nanoseconds, is not a problem because it is much shorter than the wake-up time of the SoC, which generally takes from several hundred nanoseconds to several microseconds [24], [25]. The longer sensing delay may increase the probability of the read disturbance because the critical current decreases with the sensing delay.…”

Section: Sensing Delay Simulation and Area Estimationmentioning

confidence: 99%

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

Ryu

Kim

Jung

et al. 2012

IEEE Trans. VLSI Syst.

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Recently, a magnetic tunnel junction (MTJ), which is a strong candidate as a next-generation memory element, has been used not only as a memory cell but also in spintronics logic because of its excellent properties of nonvolatility, no silicon area occupation, and CMOS process compatibility. One of the representative research areas for the spintronics logic is the zero standby leakage retention flip-flop. Conventional zero standby leakage retention flip-flops have several problems, including difficulty in design optimization among the delay, sensing current, and process variation tolerance, and the insufficient write current. In this paper, a new MTJ based retention flip-flop is presented to solve these problems. The proposed retention flip-flop is designed using industry-compatible 45-nm process technology model. The proposed retention flip-flop achieves a 41.58% reduced delay and a 67.53% lowered sensing current with a 1.06% increased area compared to the previous retention flip-flop. Index Terms-magnetic tunnel junction (MTJ) logic, nonvolatile flip-flop, retention flip-flop, spintronics logic.

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A 1.92¿s-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors

Cited by 12 publications

References 0 publications

Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs

Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs

R-FFT: Function Split at IFFT/FFT in Unified LTE CRAN and Cable Access Network

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop

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