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A nonvolatile Magnetic Flip-Flop (MFF) primitive cell for SoC design libraries has been developed using a unique MRAM process. It has high design compatibility with conventional CMOS LSI designs. MFF maximum frequency was estimated to be 3.5 GHz, which is comparable to that of a normal CMOS DFF. An MFF test chip was fabricated with the process. The chip's functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of SoCs dramatically.

A magnetic tunnel junction (MTJ)-based logic-inmemory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.

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Recently there has been increased demand for not only ultra-low power, but also high performance, even in standby-power-critical applications. Sensor nodes, for example, need a microcontroller unit (MCU) that has the ability to process signals and compress data immediately. A previously reported 130nm CMOS and FeRAM-based MCU features zero-standby power and fast wakeup operation by incorporating FeRAM devices into logic circuits [1]. The 8MHz speed, however, was not sufficiently high to meet application requirements, and the FeRAM process also has drawbacks: low compatibility with standard CMOS, and write endurance limitations. A spintronics-based nonvolatile integrated circuit is a promising option to achieve zero standby power and high-speed operation, along with compatibility with CMOS processes. In this work, we demonstrate a fully nonvolatile 16b MCU using 90nm standard CMOS and three-terminal SpinRAM technology. It achieves 20MHz, 145μW/MHz operation with a 1V supply in the active state, and 4.5μW intermittent operation with 120ns wakeup time and 0.1% active ratio, without forwarding of re-boot code from memory. The features provide sufficiently long battery life to achieve maintenance-free sensor nodes.An overview of the nonvolatile microcontroller is shown in Fig. 10.5.1. The microcontroller comprises a 16b RISC architecture CPU core (compatible with the MSP430 instruction set [2]), a 64KB RAM/ROM-unified SpinRAM macro, a power-management module (PMM), a unified clock system (UCS), two timers (A and B), a 12b ADC, a 32b multiplier (MPY), two universal serial interfaces (USCI-A and B), a direct memory access (DMA) module, and eight I/O ports (P1-8). The SpinRAM macro consists of 2-transistor 1-magnetic-tunnel-junction (2T1MTJ) memory cells [3], and it has some redundant words and columns to replace defective cells, and an error check and correction (ECC) circuit for write failures. To eliminate backup/restore overhead through the memory bus, 4,072 nonvolatile magnetic flip-flops (MFFs [4]) are employed to capture the context of the CPU. Two instructions, "SAVE" and "LOAD", allow software to flexibly backup/restore to/from the MFFs. The supply voltage range (DV CC ) is 1.8 to 3.3V and the 1V internal power supply (V CORE ) is provided by a DC/DC converter in the PMM. The chip has 11 power domains (PDs), where the power supply (V PD ) in each PD is isolated from V CORE by an internal power switch. Each logic core belongs to a PD so that cores can be individually turned off when they are not needed. The microcontroller supports three low-power modes: standby mode, power-gating (PG) mode, and sleep mode. In standby mode, all cores remain on, and the main clock is gated, and leakage power is 117μW. In PG mode, the power-switch status of the power domains is controlled by the PMM, and 1.6μW static power is consumed when all cores are turned off. In sleep mode, the DC/DC converter is turned off and the static power is zero.The schematic of our three-terminal MTJ is shown in Fig. 10.5.2. The MTJ uses spin-torque s...