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A compact 6-input lookup table (LUT) circuit using nonvolatile logic-in-memory (LIM) architecture with series/parallel-connected magnetic tunnel junction (MTJ) devices is proposed for a standby-power-free field-programmable gate array. Series/parallel connections of MTJ devices make it possible not only to reduce the effect of resistance variation, but also to enhance the programmability of resistance values, which achieves a sufficient sensing margin even when process variation is serious in the recent nanometer-scaled VLSI. Moreover, the additional MTJ devices do not increase the effective chip area because the configuration circuit using MTJ devices is simplified and these devices are stacked over the CMOS plane. As a result, the transistor counts of the proposed circuit are reduced by 62% in comparison with those of a conventional nonvolatile LUT circuit where CMOS-only-based volatile static random access memory cell circuits are replaced by MTJ-based nonvolatile ones.

A magnetic tunnel junction (MTJ)-based logic-inmemory hardware accelerator LSI with cycle-based power gating is fabricated using a 90 nm MTJ/MOS process on a 300 mm wafer fabrication line for practical-scale, fully parallel motion-vector prediction, without wasted power dissipation. The proposed nonvolatile LSI is designed by establishing an automated design environment with MTJ-based logic-circuit IPs and peripheral assistant tools, as well as a precise MTJ device model produced by the fabricated test chips. Through the measurement results of the fabricated LSI, this study shows both the impact of the power-gating technique in a fine temporal granularity utilizing the non-volatility of the MTJ device and the effectiveness of the established automated design environment for designing random logic LSI using nonvolatile logic-in-memory.

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