Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium oxide (MgO) barrier MTJs are used to take advantage of their high tunnel magneto-resistance (TMR) ratio and spin-injection write capability. The MOS transistors are fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The basic operation of the full adder is confirmed.

The reliability issues of Flash electrically erasable programmable read-only memory (Flash EEPROM) are reviewed in this paper. The reduction of the memory cell size and improvement in the reliability have been realized by several breakthroughs in the device technology; in particular, the reliability of the ETOX and NAND structure EEPROM will be discussed in detail. Flash EEPROM is expected to be a very promising device for a large nonvolatile memory market. One of the most promising applications is the replacement of the conventional magnetic hard disk by nonvolatile memories.

By conducting a 1200 • C vacuum annealing of a 3C-SiC(111) ultrathin film preformed on a Si(110) surface, we have succeeded in forming a graphene layer on a Si substrate. Raman-scattering spectrum from this surface presents a distinct 2D band, whose deconvolution into four subcomponents indicates that the film mostly consists of a two-layer graphene. The peak position is blue-shifted from that of a free-standing graphene formed by a mechanical exfoliation method, suggesting a compressive stress in the film.

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