Few-layers graphene is epitaxially grown on silicon substrates via SiC thin films inserted in between. We have conducted a detailed structural characterization of this graphene-on-silicon (GOS) material by Raman spectroscopy and transmission-electron microscopy, to obtain insights into the impacts of process parameters on defect formation. Results suggest that defects in graphene preferentially dwell at steps. Future flattening of the SiC surface, prior to graphene growth, is thus expected to contribute to the improvement of GOS quality.

By conducting a 1200 • C vacuum annealing of a 3C-SiC(111) ultrathin film preformed on a Si(110) surface, we have succeeded in forming a graphene layer on a Si substrate. Raman-scattering spectrum from this surface presents a distinct 2D band, whose deconvolution into four subcomponents indicates that the film mostly consists of a two-layer graphene. The peak position is blue-shifted from that of a free-standing graphene formed by a mechanical exfoliation method, suggesting a compressive stress in the film.

Epitaxial graphene on Si (GOS) using a heteroepitaxy of 3C-SiC/Si has attracted recent attention owing to its capability to fuse graphene with Si-based electronics. We demonstrate that the stacking, interface structure, and hence, electronic properties of GOS can be controlled by tuning the surface termination of 3C-SiC(111)/Si, with a proper choice of Si substrate and SiC growth conditions. On the Si-terminated 3C-SiC(111)/Si(111) surface, GOS is Bernal-stacked with a band splitting, while on the C-terminated 3C-SiC(111)/Si(110) surface, GOS is turbostratically stacked without a band splitting. This work enables us to precisely control the electronic properties of GOS for forthcoming devices.