Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

Sakimura, N.; Sugibayashi, Toshio; Nebashi, R.; Kasai, N.

doi:10.1109/jssc.2009.2023192

Cited by 149 publications

(58 citation statements)

References 16 publications

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“…While transistor counts of [4] are small, the effective area is large since CMOS inverters in the slave latch must be enlarged to drive sufficient write current, which results in large active power dissipation for the normal operation. The use of external write driver in [1,6] also causes delay and power overheads due to additional gate capacitance of their write drivers. Separation of the write driver and the sensing circuit reduces the performance overhead [5], but area overhead is more than 2.5 time higher than that of the CMOS FF.…”

Section: Evaluationsmentioning

confidence: 99%

“…In terms of recall energy, [1], [4], [6] consume relatively high recall energy since these NV-FFs utilize differential current sensing and read currents flows through two STT-MTJ/DWM devices simultaneously. Meanwhile, the pro- posed NV-FF exhibits the same degree of standby power dissipation without the power gating technique owing to its simplified circuitry.…”

Section: Evaluationsmentioning

confidence: 99%

“…The combination of nonvolatile logic circuits together with a power-gating technique where power supply of all the idle function blocks are temporally turned off, is one promising solution for the standby power problem in nanoscale CMOS technologies [1,2,3]. A nonvolatile flip-flop (NV-FF) [1,3,4,5,6] is an essential component for a nonvolatile logic LSI since temporal data of each function block must be clock-synchronized and retained during poweroff.…”

Section: Introductionmentioning

confidence: 99%

“…A nonvolatile flip-flop (NV-FF) [1,3,4,5,6] is an essential component for a nonvolatile logic LSI since temporal data of each function block must be clock-synchronized and retained during poweroff. Because temporal data in an NV-FF must be stored in a nonvolatile device every time before power-off, it is very important that the nonvolatile device has unlimited endurance as well as fast switching capability in nanoseconds.…”

Section: Introductionmentioning

confidence: 99%

“…To perform CMOS compatible high-speed operation, some MTJ-based NV-FFs operate as CMOS D-FFs during the normal operation, and MTJ read/write accesses are performed just only before power-on/off [1,4,5,6]. Fig.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

Suzuki

Sakimura

Natsui

et al. 2014

IEICE Electron. Express

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A nonvolatile flip-flop (NV-FF) is proposed for a zerostandby-power LSI using a domain-wall motion (DWM) device. Since the write current path is separated from the read current path in the DWM device, two nonvolatile memory function blocks, a write driver for storing temporal data into the DWM device, and a sense amplifier for recalling the stored data from the DWM device can be optimized independently. Moreover, the use of a nonvolatile storage cell with a DWM-device-based single-ended structure makes it possible to implement both of these functions as two CMOS inverters, which makes it possible to merge them into a CMOS delay flip-flop (D-FF) core. Since the nonvolatile storage cell is electrically separated from the D-FF core during the normal operation, there is no performance degradation. In fact, the area and the power-delay product of the proposed NV-FF are minimized compared to those of the previous works.

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