2011 IEEE International Symposium of Circuits and Systems (ISCAS) 2011
DOI: 10.1109/iscas.2011.5938235
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A 1.93 pA/√Hz transimpedance amplifier for 2.5 Gb/s optical communications

Abstract: A state-of-the-art low-noise transimpedance amplifier (TIA) for 2.5 Gb/s family is presented using IBM 0.13-µm CMOS technology. This TIA woul d be a pa rt of a homod yne detector in a quantum ke y distribution (QKD) sy stem. In this work a thorough design methodology based on a novel analytical noise optimization is presented. Also a unique method for eliminating the DC current o f the input photodiodes (PDs) is proposed. The post-layout simulation results show bandwidth of 52 kHz to 1.9 GHz, average input ref… Show more

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Cited by 11 publications
(15 citation statements)
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“…In TIA design usually common gate (CG) and/or shunt-feedback amplifier are/is employed [1][2][3][4][5][6]. The shunt-feedback TIA can provide a higher transimpedance gain as compared to CG TIA.…”
Section: Introductionmentioning
confidence: 99%
“…In TIA design usually common gate (CG) and/or shunt-feedback amplifier are/is employed [1][2][3][4][5][6]. The shunt-feedback TIA can provide a higher transimpedance gain as compared to CG TIA.…”
Section: Introductionmentioning
confidence: 99%
“…In this paper, transimpedance amplifier parameters such as transimpedance gain, power consumption and output voltage are studied in 0.35µm CMOS technology. Figure 2 shows CMOS transimpedance amplifier circuit used a push-pull inverter at the input to maximize the transconduction of amplifier [4] and increases its gain bandwidth product (GBP).…”
Section: Introductonmentioning
confidence: 99%
“…It is relatively high bandwidth and dynamic range as well as a good noise level. Figure 2 shows CMOS transimpedance amplifier circuit used a push-pull inverter at the input to maximize the transconduction of amplifier [4] and increases its gain bandwidth product (GBP). …”
mentioning
confidence: 99%
“…Input parasitic capacitances of photodiode, electro-static discharge (ESD) circuit, and input PAD at the input of TIAs primarily constrain their bandwidth and noise performances [6]. As a result, different input topologies have been proposed to relax the effect of input capacitance, such as common gate (CG) [7], regulated cascode (RGC) [6,17], common drain (CD) [8], and common source (CS) [5]. At first glance, CG and RGC topologies seem better candidates in terms of relaxing the effect of input parasitic capacitances, but high current noise contribution of the load and input transistors in these topologies, degrades the noise performance drastically [4].…”
mentioning
confidence: 99%
“…As shown in Fig. 2, we proposed [5] a TIA with capacitive feedback network for maintaining high gain and low noise at the same time. Also a circuit level solution for the DC dark current in this topology is provided.…”
mentioning
confidence: 99%