A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology

Hamzaoglu, Fatih; Arslan, Ümüt; Bisnik, Nabhendra; Ghosh, Swaroop; Lal, Manoj B.; Lindert, N.; Meterelliyoz, Mesut; Osborne, Randy B.; Park, Joodong; Tomishima, Shigeki; Wang, Yih; Zhang, Kevin

doi:10.1109/jssc.2014.2353793

Cited by 30 publications

(6 citation statements)

References 8 publications

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“…We report power for a 1.28GHz operating frequency, which is fast enough to achieve physics-limited volume rates for the full 32×32 receive aperture at any imaging depth; smaller apertures can be processed at lower frequencies (and lower power). We estimate the area and power requirements of the 12.5MB eDRAM based on reported results for a 22nm technology [4].…”

Section: Full-system Powermentioning

confidence: 99%

Tetris

West

Zhou

Dreslinski

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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High volume acquisition rates are imperative for medical ultrasound imaging applications, such as 3D elastography and 3D vector flow imaging. Unfortunately, despite recent algorithmic improvements, high-volume-rate imaging remains computationally infeasible on known platforms. In this paper, we propose Tetris, a novel hardware accelerator for ultrasound beamforming that enables volume acquisition rates up to the physics limits of acoustic propagation delay. Through algorithmic and hardware optimizations, we enable a streaming system design outclassing previously proposed accelerators in performance while lowering hardware complexity and storage requirements. For a representative imaging task, our proposed system generates physics-limited 13,020 volumes per second in a 2.5W power budget. CCS CONCEPTS • Hardware → Emerging architectures; 3D integrated circuits.;

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Section: Full-system Powermentioning

confidence: 99%

Tetris

West

Zhou

Dreslinski

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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“…Four of the eight 16 MB macros operate in parallel to deliver a cache line read or write each 1.6 GHz clock cycle. Retention time is 100 S at 93C, 1.0 V, and the 77 mm die (including charge pumps and associated supply regulators) achieves a density of 17.5 Mb/mm [5].…”

Section: Embedded-dram and On-package I/omentioning

confidence: 99%

Haswell: A Family of IA 22 nm Processors

Kurd

Chowdhury

Burton

et al. 2015

IEEE J. Solid-State Circuits

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We describe the 4th Generation Intel® Core™ processor family (codenamed "Haswell") implemented on Intel® 22 nm technology and intended to support form factors from desktops to fan-less Ultrabooks™. Performance enhancements include a 102 GB/sec L4 eDRAM cache, hardware support for transactional synchronization, and new FMA instructions that double FP operations per clock. Power improvements include Fully-Integrated Voltage Regulators ( 50% battery life extension), new low-power states (95% standby power savings), optimized MCP I/O system (1.0-1.22 pJ/b), and improved DDR I/O circuits (40% active and 100x idle power savings). Other improvements include full-platform optimization via integrated display I/O interfaces.

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“…Since gain-cell based eDRAM offers several advantages [8], registers (SRAMs partitioned into smaller banks) are replaced with non-refresh eDRAMs in the LDPC decoder. However, unlike cache applications [6]- [14], the replacement of small SRAM banks can be impractical, since the hardware overhead of additional supply voltages or voltage regulators (or charge pumps) for stable write operation and reference voltage generation in eDRAM can overshadow its inherent advantages.…”

Section: Introductionmentioning

confidence: 99%

A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

Choi

Kang

2015

IEEE J. Solid-State Circuits

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This paper presents a Viterbi-specific 2T gain cellbased embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.

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A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology

Cited by 30 publications

References 8 publications

Tetris

Tetris

Haswell: A Family of IA 22 nm Processors

A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

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