A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder

Abstract

This paper presents a Viterbi-specific 2T gain cellbased embedded DRAM (eDRAM) design for IEEE 802.11n WLAN application. In the proposed Viterbi decoder, refresh operations are completely removed in the eDRAM, by ensuring that the read-after-write period of survivor memory is shorter than the retention time of the gain cell. In order to facilitate the write operation with single-supply voltage, a beneficial read word-line (RWL) coupling technique is proposed. In this work, we also present a reference voltage generation scheme to support single-ended read operation. Thanks to the decoupled read and write structure of the gain cell, the proposed eDRAM can support dual-port operations without large area overhead, thus doubling the bandwidth of memories in the Viterbi decoder. To further reduce the area of the customized Viterbi memory, common redundant hardware between the memory peripheral and computational logics is identified and eliminated without latency overhead. The 4 bit soft-decision 64-state Viterbi decoder with 24 kb eDRAM (1-bank) is implemented in 65 nm CMOS process technology. The chip measurement results show 44% area and 39% power savings over the conventional SRAM-based Viterbi decoder implementation.

P‐channel logic 2 T eDRAM macro with high retention bit architecture

“…In the standby, the leakage currents surrounding cell devices destroy the storage as depicted. For this all‐PMOS 2 T cell, the data “1” loss in the hold is self‐protected better than the destruction of “0” storage . The voltage window between data “1” and “0” is estimated to be 403 mV at 0.5 ms and 178 mV at 1 ms after data write.…”

“…This downward action couples down the bit storage voltages through C JP , inducing preferable restoration of the data “0”. The lower “0” storage enhances the data retention time . The simulation results for different C_BD transitions in Figure illustrate the initial bit storage voltages after data write together with the required boosting capacitor (C VBB ) area to provide the corresponding V BB level.…”

“…For the competitive bit-area, the 2 T cell in the same type of MOSFETs 9-13 could be the most effective option. Moreover, to obtain high data retention, PMOS-only cells [11][12][13] would be preferable because PMOS transistors have significantly lower leakage currents over their NMOS counterparts.…”

“…The lower "0" storage enhances the data retention time. 2,13 The simulation results for different C_BD transitions in Figure 4 illustrate the initial bit storage voltages after data write together with the required boosting capacitor (C VBB ) area to provide the corresponding V BB level. In this work, V BB level is chosen to be 1.5V DD .…”

A Logic-compatible Embedded DRAM Utilizing Common-body Toggled Capacitive Cross-talk

“…The gain cell in a hybrid structure of PMOS and NMOS [8] also consumes a spacious bit-area because of large well-towell space. The 2T structure in a same type of transistors would provide most compact bit-area, but the all-PMOS 2T cells [9][10][11] may limit the read performance of the memory due to the poor channel mobility of PMOS read device.…”