P‐channel logic 2 T eDRAM macro with high retention bit architecture

Manisankar, Sivasundar; Chung, Yunchul

doi:10.1002/cta.2496

Cited by 3 publications

(3 citation statements)

References 18 publications

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“…The use of LP technology for the write transistor results in higher DRT since the transistors are in the primary data failure path. 6 In the proposed design, WWLn and WWLp are used to neutralize the effects of the applied CF and CI to the SN due to the opposing CI and CF effects from the PW and NB transistors due to the occurrence of the de-assertion of the wordlines. 9 Given that both p-type and n-type transistors are in the data write path, "1" and "0" are only written up to V DD -V Tn and V Tp , respectively.…”

Section: Proposed 5t Gc-edram Cell Structurementioning

confidence: 99%

“…5 Gain-cell embedded dynamic random-access memory (GC-eDRAM) has been popular as an alternative to conventional static random-access memory (SRAM) because of its scalability, higher area density, inherent two-port operation, non-destructive read operation, and low leakage consumption compared to SRAM. 6 Nonetheless, the major drawback of gain-cell memories is the need for periodic refresh cycles, resulting in a considerable amount of refresh power and thus retention power consumption that limits the availability percentage. Consequently, the data retention time improving reduces power consumption.…”

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confidence: 99%

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A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

Sany

Ebrahimi

2021

Circuit Theory & Apps

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Conventional static random‐access memory (SRAM) suffers from high leakage power in advanced complementary metal‐oxide‐semiconductor nodes. Meanwhile, gain‐cell embedded dynamic random‐access memory (GC‐eDRAM) is an area‐efficient alternative to SRAM, although it requires periodic refresh cycles. In this regard, this study proposes a fin field‐effect transistor (FinFET)‐based 5T GC‐eDRAM bitcell that addresses the leakage power issue of SRAM while avoiding the bandwidth‐consuming refreshes of GC‐eDRAM. Furthermore, for the feasibility of scaling down transistors, the gain‐cell design is based on the FinFET, which overcomes short‐channel problems. The proposed 5T bitcell provides additional internal feedback relative to the 4T all‐nMOS fully depleted‐silicon on insulator (FD‐SOI) gain cell to ensure the static retention of both “1” and “0” data. The 2‐kB array was simulated by employing a 7‐nm FinFET predictive technology model (PTM) using HSPICE. The simulation results show that the proposed 5T bitcell (at 0.7 V) enables over 13× smaller data retention power and 10× area reduction compared to the 4T all‐nMOS GC‐eDRAM cell in a 28‐nm FD‐SOI technology.

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Section: Proposed 5t Gc-edram Cell Structurementioning

confidence: 99%

mentioning

confidence: 99%

A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

Sany

Ebrahimi

2021

Circuit Theory & Apps

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“…The eDRAM has the benefit of higher speed and lower power consumption compared with SRAM. [1][2][3][4][5][6][7] However, the conventional eDRAM cell, which consists of one-transistor and one capacitor (1T-1C), has confronted the limitation of capacitor shrinking. Therefore, a capacitorless one-transistor DRAM (1T-DRAM) has been researched recently as a means to overcome the limitations of the conventional 1T-1C DRAM.…”

Section: Introductionmentioning

confidence: 99%

Polycrystalline silicon metal-oxide-semiconductor field-effect transistor-based stacked multi-layer one-transistor dynamic random-access memory with double-gate structure for the embedded systems

Jang

Yoon

Cho

et al. 2020

Jpn. J. Appl. Phys.

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In this work, a polycrystalline silicon (poly-Si) double-gate metal-oxide-semiconductor field-effect transistor-based stacked multi-layer (ML) onetransistor dynamic random-access memory for the embedded memory is proposed using technology computer-aided simulation. Although poly-Si has advantages of low-cost fabrication and implementation of three-dimensional structure, poly-Si devices suffer from low on-state current (I on ) due to the low mobility and the scattering by the grain boundary (GB) trap. The stacked ML structure is proposed to improve low I on . As a result of simulation, the ML device obtained a high I on of 87.92 μA μm −1 . Owing to the enhancement of I on , the ML achieved a high SM of 30.44 μA μm −1 . A retention time (RT) of the proposed ML device in the simulation exhibited 2.94 ms even at a high temperature of 358 K. Moreover, the proposed ML device demonstrates superior reliability in terms of memory operations (RT >100 μs) for randomly distributed GBs.

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Logic-Compatible Embedded DRAM Architecture for Multifunctional Digital Storage and Compute-in-Memory

Kim,

Chung

2024

Applied Sciences

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The compute-in-memory (CIM) which embeds computation inside memory is an attractive scheme to circumvent von Neumann bottlenecks. This study proposes a logic-compatible embedded DRAM architecture that supports data storage as well as versatile digital computations. The proposed configurable memory unit operates in three modes: (1) memory mode in which it works as a normal dynamic memory, (2) logic–arithmetic mode where it performs bit-wise Boolean logic and full adder operations on two words stored within the memory array, and (3) convolution mode in which it executes digitally XNOR-and-accumulate (XAC) operation for binarized neural networks. A 1.0-V 4096-word × 8-bit computational DRAM implemented in a 45-nanometer CMOS technology performs memory, logic and arithmetic operations at 241, 229, and 224 MHz while consuming the energy of 7.92, 8.09, and 8.19 pJ/cycle. Compared with conventional digital computing, it saves energy and latency of the arithmetic operation by at least 47% and 46%, respectively. For VDD = 1.0 V, the proposed CIM unit performs two 128-input XAC operations at 292 MHz with an energy consumption of 20.8 pJ/cycle, achieving 24.6 TOPS/W. This marks at least 11.9× better energy efficiency and 38.8× better delay, thereby achieving at least 461× better energy-delay product than traditional 8-bit wide computing hardware.

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P‐channel logic 2 T eDRAM macro with high retention bit architecture

Cited by 3 publications

References 18 publications

A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

Polycrystalline silicon metal-oxide-semiconductor field-effect transistor-based stacked multi-layer one-transistor dynamic random-access memory with double-gate structure for the embedded systems

Logic-Compatible Embedded DRAM Architecture for Multifunctional Digital Storage and Compute-in-Memory

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