A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

Sany, Bahareh Seyedzadeh; Ebrahimi, Behzad

doi:10.1002/cta.3171

Cited by 4 publications

(2 citation statements)

References 23 publications

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“…In the research work [12], Changmin Lee et.al propose a Non-Volatile Dual In-line Memory Module architecture that incorporates several system-wide techniques to enable nondeterministic timing, specifically asynchronous timing, on synchronous DDR4 memory interfaces. To validate our proposal, we develop a functional prototype of the memory architecture on an x86-64 server system.…”

Section: International Journal On Recent and Innovation Trends In Com...mentioning

confidence: 99%

Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC

Shravan,

Fatima,

Sekhar

2023

IJRITCC

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Emerging memory technologies, such as Gain Cell-embedded Dynamic Random Access Memory (GC-eDRAM), play an essential part in the process of improving the overall performance of current multi-processor systems. GC-eDRAM, on the other hand, has its own set of distinct issues, particularly with regard to refresh operations. The number of cores and threads in contemporary processors continues to expand, which in turn leads to an increase in the number of concurrent refresh requests. This might cause contention, which in turn can lead to a possible performance decrease. In this article, we present an efficient arbitration method that was developed in order to precisely address the issues that are associated with numerous requests for a refresh in GC-eDRAM. This method takes use of the inherent parallelism of GC-eDRAM modules to make it possible to execute simultaneous refresh operations. As a result, contention is effectively reduced, and the overall performance of the system is improved. We provide a new arbitration method that prioritizes the pending refresh requests according to their level of urgency and optimizes the allocation of GC-eDRAM resources in order to guarantee that refresh operations are carried out in an effective manner. Our method modifies the arbitration priority in a dynamic manner according to the characteristics of the active workload. These characteristics include the request arrival rate, memory access patterns, and data location, among other considerations.

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Section: International Journal On Recent and Innovation Trends In Com...mentioning

confidence: 99%

Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC

Shravan,

Fatima,

Sekhar

2023

IJRITCC

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“…According to the level of performance requirements of various task requirements [2][3][4], "level matching" should be adopted to allow the chip to work in its "comfort zone" to achieve the maximum energy consumption ratio range [5][6][7][8][9]. The following uses some common "high and low matching" strategies to introduce the lowpower chip architecture design framework of this design [10].…”

Section: Introductionmentioning

confidence: 99%

Chip Architecture Design Management Based on Low-Power Multitasking Simulation

Zhang,

Sun

2023

Advances in Transdisciplinary Engineering

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From the aspects of low-power DSP design, low-power SOC design, and low-power power switch design, this paper proposes a chip architecture “high-low matching” scheme for low-power multitasking requirements. The low-power DSP design starts with operating voltage and operating frequency control, and uses three low-power modes, PD1, PD2, and PD3; the low-power SOC design carries out low-power mode management from the clock control of APB and AHB bus; In terms of low-power power switch design, no-load low-power control, and input under-voltage protection, output over-voltage protection, over-temperature protection, and output over-current protection are implemented. The paper proposes different low-power control modes. After the evaluation of the built test platform, it is proved that the design of the scheme is reasonable, and it can realize the engineering application of low-power multi-task management.

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Transition metal dichalcogenide FET‐based dynamic random‐access memory

Raoofi,

Gholipour

2024

Circuit Theory & Apps

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Transition metal dichalcogenide field‐effect transistors (TMDFETs) as a replacement for conventional metal–oxide–semiconductor field‐effect transistors (MOSFETs) have attracted the attention of researchers in recent years. The efficiency of these devices should be investigated in different aspects in digital systems. One of the important components of such systems is dynamic random‐access memory (DRAM), which is used in most computers and many electronic systems as the main memory due to its small area and simple structure, compared to static memory (SRAM) cells. In this paper, a regular DRAM cell is designed based on TMDFET devices and its performance is compared with a similar cell in conventional MOSFET technology from various aspects, including DRAM‐specific timing characteristics considering changes in design and environmental parameter variations using Monte Carlo simulations. The simulations have been carried out in HSPICE with 16 nm technology under fair conditions for different technologies, at room temperature with a 0.7‐V power supply. The results show that the TMD‐DRAM has 3.55×, 3.08×, and 2.23× faster bitline recovery, merge time, and sense time than Si‐MOS‐DRAM, respectively. The Si‐MOS‐DRAM, on the other hand, has 1.65× faster write time compared to TMD‐DRAM. However, TMD‐DRAM consumes overall higher power than Si‐MOS‐DRAM, and shows higher average read power variability with the σ/μ = 0.476. The TMD‐DRAM also shows higher variability in the studied timing characteristics than Si‐MOS‐DRAM except merge and sense times.

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A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

Cited by 4 publications

References 23 publications

Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC

Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC

Chip Architecture Design Management Based on Low-Power Multitasking Simulation

Transition metal dichalcogenide FET‐based dynamic random‐access memory

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