A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm

Liu, Huasen; Wu, Danyu; Zhou, Lei; Luan, Jian; Guo, Xuan; Wu, Jin; Liu, Xinyu

doi:10.1587/elex.16.20181150

IEICE Electron. Express

2019

DOI: 10.1587/elex.16.20181150

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A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm

Huasen Liu

Danyu Wu

Lei Zhou

et al.

Abstract: In this paper, a 1-GS/s 12-bit pipelined folding analog-to-digital converter (ADC) fabricated in 40 nm CMOS technology is presented. A new encoding algorithm based on distributed quantization is proposed to simplify the quantization process of the structure with odd folding factor and reduce the hardware consumption of the circuit. The ADC achieves spurious free dynamic range (SFDR) > 72 dB and signal-to-noise and distortion ratio (SNDR) > 57 dB in low input frequencies.

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Cited by 2 publications

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A 12-bit 2.32GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer

Guo,

Li,

Fang

et al. 2023

IEICE Electron. Express

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This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-todigital converter (ADC) implemented in 28 nm CMOS. To achieve highlinearity at several GS/s, a pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR hybrid architecture with dual-channel sampling multiplying digital-to-analog converter (MDAC) and one shared flash sub-ADC is used exploiting a simple calibration. The ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 55.68dB and a spurious-free-dynamic-range (SFDR) of 72.18dB at 1125MHz input and consumes 175 mW.

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A 12-bit 2.32GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer

Guo,

Li,

Fang

et al. 2023

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

A 12-Bit 2.4 GS/s Four-Channel Pipelined ADC with a Novel On-Chip Timing Mismatch Calibration

Jia

Guo

et al. 2020

Electronics

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This paper presents a 12-bit 2.4 GS/s analog-to-digital converter (ADC) employing four time-interleaved (TI) pipelined channels with a novel on-chip timing mismatch calibration in 40 nm CMOS process. TI architecture can increase the effective sampling rate of ADC but the dynamic performance of TI-ADC system is seriously degraded by offset, gain, and timing mismatches among the channels. Timing mismatch is the most challenging barrier among these mismatches due to the difficulty and complexity of its detection and correction. An automatic wideband timing mismatch detection algorithm is proposed for achieving a wide frequency range of timing mismatch detection without complex calculations. By adopting the proposed mismatch-free variable delay line (VDL), the full-scale traversal timing mismatch correction accomplishes an accurate result without missing codes. Measurement results show that the spurious free dynamic range (SFDR) of the prototype ADC is improved from 55.2 dB to 72.8 dB after calibration at 2.4 GS/s with a 141 MHz input signal. It can achieve an SFDR above 60 dB across the entire first Nyquist band based on the timing mismatch calibration and retiming technology. The prototype ADC chip occupies an area of 3 mm × 3 mm and it consumes 420 mW from a 1.8 V supply.

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A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm

Cited by 2 publications

References 13 publications

A 12-bit 2.32GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer

A 12-bit 2.32GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer

A 12-Bit 2.4 GS/s Four-Channel Pipelined ADC with a Novel On-Chip Timing Mismatch Calibration

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