A 1 to 18 GHz out of phase combiner

Jouanneau-Douard, M.; Brouzes, H.; Bionaz, S.; Levy, David H.

doi:10.1109/mcs.1992.186004

Cited by 4 publications

(4 citation statements)

References 4 publications

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“…17 shows that, as predicted by theory, the noise power density is higher at small offsets from the carrier and decreases as the frequency offset from the carrier becomes higher due to 1/f noise in the input circuit.…”

supporting

confidence: 59%

“…An interesting solution is suggested in reference [17]. Two MOS transistors, one in common-drain and the other in common-source configuration are connected as shown in If V(in_n)=0 and the RF voltage is applied at in_p only, one can write:…”

Section: Active Balunmentioning

confidence: 99%

“…12 Symbol constellations for QPSK, 16QAM and 64QAM2.7 I/Q imbalance and noise impact on EVMEVM is a widely accepted measure of the quality of a digitally modulated signal.EVM is defined as shown in(17) …”

mentioning

confidence: 99%

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Wideband Up-Converting Mixer for Digital Communications Implemented in 130nm CMOS Technology

Patulea¹

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The drive for lower manufacturing cost has led to the use of CMOS technology for highly integrated radios dedicated to the consumer market. Based on the observation that the wireless devices cover a wide range of frequencies from 700MHz to almost 6GHz, this work proposes the implementation of a wide band up-converting mixer that can be used as a building block in any device that operates in this frequency range. The intent is to cover more than a decade for the output modulated carrier without any internal band switching.This thesis presents the design methodology and silicon implementation of a 0.13μm CMOS up-conversion mixer for wireless applications. The design approach is simulation based while maintaining the appropriate reference to the theory.The novelty of this work mainly consists in the implementation of the wide band digital phase shifter on the same chip with the analog mixer/multiplier cells. The design methodology allows a cost effective implementation of a fully integrated solution that requires 1.2x1.55mm of silicon and it can be used in any wireless device that transmits digitally modulated data.The following components were designed, simulated then integrated on chip: wideband digital phase shifter, two Gilbert cells for the I and Q paths, wideband active balun and biasing cells.The modular design and individual testing of each sub-block allowed for effective integration and debugging in the initial development phase.At the end of this exercise, one of the fabricated silicon chips was successfully tested in the lab. Detailed measurement and test results are provided in Chapter 5 iv

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confidence: 59%

Section: Active Balunmentioning

confidence: 99%

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Wideband Up-Converting Mixer for Digital Communications Implemented in 130nm CMOS Technology

Patulea¹

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“…However this implementation exhibits high insertion loss and phase unbalance issues. In another work, a 180° combiner based on the totem pole configuration was presented [14]. Anyway, due to Common Drain connection and losses in the lumped element matching networks, an insertion gain is not recorded.…”

Section: Introductionmentioning

confidence: 99%

Distributed active balun with improved linearity performance

Palomba

Palombini

Colangeli

et al. 2015

2015 German Microwave Conference

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A new active balun topology is introduced allowing to overcome gain and bandwidth limitations of traditional out-of-phase power dividers. Proposed architecture employs distributed circuits as Artificial Transmission Line Pair (ATLP) and Split Drain Distributed Amplifier (SDDA) for achieving a broadband signal balancing and featuring a positive insertion gain too. In this contribution a complete theoretical analysis for the ATLP and SDDA principle of operation is provided together with the description of the actual design flow. MMIC test vehicle operating on the multi-octave frequency range 2-18 GHz proves the effectiveness of presented topology

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A systematic method for nonlinear analysis of a class of FET circuits

Losada¹,

Haigh²,

Radmore³

1993 IEEE International Symposium on Circuits and Systems

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The square-law relationship between the drain current and the gatesource voltage of an FET implies that a circuit comprising FETs has, in general, a nonlinear relationship between its port variables. In this paper, the small-signal admittance matrix analysis technique is extended to allow systematic by-hand analysis of the linear and nonlinear behaviour of FET circuits. A constraint on circuit architecture which ensures that the resulting network functions are rational is derived. Examples of analysis are given. The analysis method will be a valuable tool for the development of novel circuits, both linear (eg amplifiers, isolators, circulators, signal splitters and combiners) and nonlinear (eg multipliers and frequency doublers). It can also allow cataloging and analysis of all possible circuits of a given complexity.

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A 1 to 18 GHz out of phase combiner

Cited by 4 publications

References 4 publications

Wideband Up-Converting Mixer for Digital Communications Implemented in 130nm CMOS Technology

Wideband Up-Converting Mixer for Digital Communications Implemented in 130nm CMOS Technology

Distributed active balun with improved linearity performance

A systematic method for nonlinear analysis of a class of FET circuits

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