A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from −45°C to 125°C

Kamath, Umanath; Cullen, Edward; Jennings, John; Cical, Ionut; Walsh, Darragh; Lim, Peng; Farley, Brendan; Staszewski, Robert Bogdan

doi:10.1109/esscirc.2018.8494284

Cited by 7 publications

(8 citation statements)

References 5 publications

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“…In circuits where MOSFETs operate in the sub‐threshold region (e.g. sub‐µA currents) and in low current BGRs, the strong temperature variations of diffusion leakage currents near/above 125°C render some form of calibration and/or trimming imperative, as corroborated by multiple recent reports [2,4,6,10,12,14] (also see Table , Appendix ). The implementation of the foregoing considerations in conjunction with those set forth in [16] has yielded key analogue CMOS building blocks (e.g.…”

Section: Junction Leakage Current Considerationsmentioning

confidence: 74%

“…Putting Equation (9) into Equation (2) indicates that when the MOSFET is biased at this fixed gate-source voltage, its current is…”

Section: Saturation Region Conditions For Minimum |(Di D /Dt )|mentioning

confidence: 99%

“…A survey of the literature over the past 2 decades reveals a trend in the development of system-on-chip (SoC) integrated circuits geared towards the Internet of Things (IoT), wearable and wireless devices, and generally 'smart', less-consuming, and more power-efficient electronics. The need for accurate references constrained by low voltage (<1 V), current, and power allowances (<1 nW) has spurred a variety of calibration techniques to achieve BGR curvature correction [2,3] and poly and metal-shunt resistor trimming [4,5] by means of dynamic error correction methods [5], digitally assisted [6,7], programmable [8,9], or otherwise. A representative sample of the state-ofthe-art for such methods and diversity of applications thereof [2][3][4][5][6][7][8][9][10][11][12][13] can be found in Table A1 (see Appendix 2).…”

Section: Introductionmentioning

confidence: 99%

“…The need for accurate references constrained by low voltage (<1 V), current, and power allowances (<1 nW) has spurred a variety of calibration techniques to achieve BGR curvature correction [2,3] and poly and metal-shunt resistor trimming [4,5] by means of dynamic error correction methods [5], digitally assisted [6,7], programmable [8,9], or otherwise. A representative sample of the state-ofthe-art for such methods and diversity of applications thereof [2][3][4][5][6][7][8][9][10][11][12][13] can be found in Table A1 (see Appendix 2).…”

Section: Introductionmentioning

confidence: 99%

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Thermal synergies in 50 nanometer CMOS and below

Shoucair

2021

IET Circuits, Devices & Syst

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An analysis of the metal oxide semiconductor field effect transistor (MOSFET) in strong inversion indicates two bias regions, in each of its triode and saturation conditions, whose distinct properties are elaborated and shown to lead to simple, systematic, design procedures for achieving low temperature coefficient (TC) voltages (<�100 ppm/°C) and currents (<�400 ppm/°C) in standard complementary metal oxide semiconductor (CMOS) processes over wide temperature spans (-55°C to þ163°C). The method involves combining devices with the same polarity (e.g. n-channel MOSFETs in p-well processes and vice versa) in a judicious manner suggested by theory, which side-steps the need for disparate elements such as resistors, diodes, and bipolar transistors, whose thermal variations are more difficult to model and offset mutually; the more so, the wider the temperature range. The close agreement between analysis and simulations (BSIM4) is illustrated by representative circuit design examples embodying the proposed principles. The concepts set forth offer advantages as generally accrue from design simplification and reduced circuit complexity; they are scalable as industrial silicon CMOS processeswhich are not optimised for extended thermal operation-evolve below 50 nm, and suitable to other technologies which find applications in the automotive, aviation, aerospace, energy, and geophysical sensing sectors, among others, such as silicon carbide, wherein MOSFETs can operate above 300°C. Et ignem regunt numeri (Plato) [1]. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Section: Junction Leakage Current Considerationsmentioning

confidence: 74%

“…Putting Equation (9) into Equation (2) indicates that when the MOSFET is biased at this fixed gate-source voltage, its current is…”

Section: Saturation Region Conditions For Minimum |(Di D /Dt )|mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Thermal synergies in 50 nanometer CMOS and below

Shoucair

2021

IET Circuits, Devices & Syst

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“…Traditional voltage reference circuits, such as the well known bandgap voltage reference (BGR), use the bipolar junction transistor (BJT) temperature dependence in order to generate a proportional to absolute temperature (PTAT) voltage, which is then utilized in order to produce a first-order temperature compensation scheme [2,7]. Subsequent approaches focus on partially canceling the BJT's base-emitter voltage non-linearities, in order to provide a higher-order, non-linear compensation [8][9][10][11][12][13]. The penalty of this approach is the higher design complexity and increased power consumption.…”

Section: Introductionmentioning

confidence: 99%

Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions

et al. 2019

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The radiation tolerance of subthreshold reference circuits for space microelectronics is presented. The assessment is supported by measured results of total ionization dose and single event transient radiation-induced effects under γ -rays, X-rays, protons and heavy ions (silicon, krypton and xenon). A high total irradiation dose with different radiation sources was used to evaluate the proposed topologies for a wide range of applications operating in harsh environments similar to the space environment. The proposed custom designed integrated circuits (IC) circuits utilize only CMOS transistors, operating in the subthreshold regime, and poly-silicon resistors without using any external components such as compensation capacitors. The circuits are radiation hardened by design (RHBD) and they were fabricated using TowerJazz Semiconductor’s 0.18 μm standard CMOS technology. The proposed voltage references are shown to be suitable for high-precision and low-power space applications. It is demonstrated that radiation hardened microelectronics operating in subthreshold regime are promising candidates for significantly reducing the size and cost of space missions due to reduced energy requirements.

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Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference

Colombo

Yin

et al. 2022

IEEE Access

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A Bandgap reference (BGR) circuit with a new high-order curvature-compensation technique is proposed in this paper. The curvature method operates by adding up two correction voltages. The first one is proportional to the difference in gate-source voltages of two MOS transistors ( V GS ) operating in weak inversion mode, while the second one (V NL ) is generated using a nonlinear current created by a piecewiselinear circuit. To improve the power supply rejection ratio (PSRR) and the line regulation performance, a lowpower pre-regulator isolates the circuit power supply and BGR output. Additionally, the chopping technique reduces the output voltage noise and offset. Consequently, the overall PVT robustness of the proposed circuit is significantly improved. The circuit was implemented using a thick-oxide transistor in a standard 0.18 µm CMOS technology with a 3.3 V power supply voltage. The silicon results exhibit a temperature coefficient of 5-15 ppm/ • C in the temperature range of −10 • C to 110 • C, whereas the simulated results demonstrate a similar performance within the temperature range of −40 • C to 150 • C. The supply current consumption is 150 µA, and the chip area is 0.56 × 0.8 mm 2 . The measured peak noise at the output is 1.42 µV/ √ Hz @320 Hz, the measured PSRR @ 1 kHz is −80 dB, and the line regulation performance is 10 ppm/V, making the proposed circuit suitable for applications requiring low noise, high-order temperature compensation, and robust PVT performance.INDEX TERMS Pre-regulator, BGR, curvature compensation, low-power operation, low area, subthreshold, temperature coefficient.

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A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from −45°C to 125°C

Cited by 7 publications

References 5 publications

Thermal synergies in 50 nanometer CMOS and below

Thermal synergies in 50 nanometer CMOS and below

Low-Power, Subthreshold Reference Circuits for the Space Environment: Evaluated with γ-rays, X-rays, Protons and Heavy Ions

Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference

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