A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications

Abstract

The advent of the third generation of wireless applications creates a need for processing modules that simultaneously display high computational performance, ultra low-energy consumption and a high degree of flexibility and adaptability. The flexibility and adaptability is a necessity in the presence of multiple and evolving standards, and increases quality-of-service in the presence of dynamically evolving conditions. Reconfigurable processors offer the advantage of combining flexibility and low-energy by providing a direct spatial mapping from algorithm to architecture, hence reducing the control overhead typically associated with instructionset processors.The Pleiades processor approach combines an on-chip microprocessor with an array of heterogeneous programmable computational units of different granularities (called satellite processors) connected by a reconfigurable interconnect network (Figure 4.1.1) [1].The microprocessor supports the control-intensive components of the applications as well as the reconfiguration, while repetitive and regular data-intensive loops (henceforth referred to as kernels) are directly mapped on the array of satellites by configuring the satellite parameters and the interconnections between them (Figure 4.1.2). Synchronization between the satellite processors is by a data-driven communication protocol in accordance with the dataflow nature of the computations performed in the kernels. A generalized interface wrapper is placed around each satellite processor to comply with the communication protocol. This spatial programming approach results in energy efficiency levels of 50-100MIPS/mW, at least an order of magnitude better than what can be accomplished in comparable DSP processors, by exploiting the locality of the computations and the correlations within data streams, and by distributing the control.A prototype processor is implemented targeting the domain of voice processing (and related applications) for wireless devices. The Maia processor (Figure 4.1.3) combines an ARM8 core with 21 satellite processors: two MACs, two ALUs, eight address generators, eight embedded memories (4 512x16b, 4 1Kx16b), and an embedded lowenergy FPGA [3]. Through an interface control unit, ARM8 configures the memory-mapped satellites using a 32b configuration bus, and communicates data with satellites using 2 pairs of IO interface ports and direct memory reads/writes. Connections between satellites are through a 2-level hierarchical mesh-structured reconfigurable interconnect network. The 210-pin chip contains 1.2M transistors and measures 5.2x6.7mm 2 in 0.25µm 6-metal CMOS (Figure 4.1.4).The embedded ARM8 core is optimized for low-energy operation, and operates under variable supply voltages [2]. Both the dualstage pipelined MAC (including shift/round/saturate functions) and the ALU can be configured to handle a range of operations. The address generators and embedded memories are distributed to supply multiple parallel data streams to the computational elements. The address generator features a sm...

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