A pipelined configurable gate array for embedded processors

Lodi, Andrea; Toma, M.; Campi, Fabio

doi:10.1145/611819.611822

Cited by 9 publications

(8 citation statements)

References 14 publications

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“…An efficient and easy integration of a reconfigurable block inside a processor core is normally a hard task because of the intensive interaction between the two parts. In the case of the PiCoGA, the adoption of a clear computational model and a fixed frequency approach allowed quite an easy integration of the array, with only slight modifications of the original design of the processor [4].…”

Section: Resultsmentioning

confidence: 99%

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A Multi-Context Pipelined Array for Embedded Systems

Lodi

Mucci

Bocchi

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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The integration of a reconfigurable device into complex SoCs is a common request aimed at adding software programmable efficient computational blocks to a system. In such environment a traditional approach in FPGA design could not meet the need for an easy-to-use and easy-to-integrate device. This paper presents the PiCoGA-II reconfigurable datapath which has been designed as a multi-context array to provide fast dynamic reconfiguration. Architectural choices to reduce the area overhead of this approach are described. A reconfigurable dedicated control unit provides a clear interface for an easy integration of the device together with a hardware support for a programming flow starting from a sequential high-level language. The logic cells have been redesigned with respect to the previous version, to improve their computational efficiency and flexibility. The PiCoGA-II has been fabricated in 0.13µm CMOS technology. The implementation of several MPEG-2 kernels shows that the multi-context array has a computational density which is 2x higher than an equivalent single-context one and is 2x higher than a Virtex-II FPGA when all the 4 contexts are utilized.

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Section: Resultsmentioning

confidence: 99%

“…Based on the original computational model [4], in this paper we present a new embedded datapath, called PiCoGA-II, where the architecture has been completely redesigned adopting innovative solutions in order to obtain a dense and fast multi-context reconfigurable device.…”

Section: Introductionmentioning

confidence: 99%

A Multi-Context Pipelined Array for Embedded Systems

Lodi

Mucci

Bocchi

et al. 2006

2006 International Conference on Field Programmable Logic and Applications

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“…It is composed as pipelined stages, in a fashion similar to the PiCoGA architecture [21]. Figure 3 shows a 3 × 4 CGRA array.…”

Section: Architecture Modeling and Generationmentioning

confidence: 99%

Fast prototyping environment for embedded reconfigurable units

Picard

Lagadec

2011

6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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In order to cope with the increasing complexity of embedded applications as well as their fast evolution, flexible systems with high-performance are mandatory. In this context, reconfigurable system-on-chip solutions that meet application needs have become common. However, the innovation race shrinks time-to-market and puts high pressure on designers. Therefore designers need appropriate methodologies and tools to efficiently perform design space exploration of reconfigurable units. This paper addresses this issue with an ADL-based toolsuite for fast prototyping of reconfigurable units. Starting from a high-level model it supports design space exploration for different architectural solutions, to produce an hardware prototype and to generate the applicative tools for exploitation. Benefits and feasability of the approach are demonstrated by the complete prototyping and implementation of a reconfigurable unit supporting ressources virtualization.

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“…This technique has been extensively applied in the design of the PiCoGA configurable device [15], which has been implemented on silicon in 0.13µm STMicroelectronics technology. Though the dual threshold approach has been adopted, yet considerable power dissipation due to leakage remains, which will considerably increase scaling to technology below 90nm.…”

Section: Introductionmentioning

confidence: 99%

Combining low-leakage techniques for FPGA routing design

Lodi

Ciccarelli

Giansante

2005

Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays

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Reconfigurable architectures are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to 90nm technology and below, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. We propose to combine super cut-off, body biasing and multi-threshold techniques to reduce the leakage current of programmable interconnections, which give by far the main contribution to static power dissipation. Super cut-off (gate biasing) technique is well suited for high-speed pass-transistors, while body biasing can be adopted for large buffers. On the other hand high threshold transistors can be used where delays are not critical. We show the design of SRAM cells generating the required high swing signals for gate-biased and body-biased transistors without affecting transistor reliability. Compared to a standard design the adoption of a mixed technique reduces routing leakage by more than one order of magnitude with only a 5% increase in switch delay and a 9% in tile area, while with respect to a full dual-threshold approach, delay is reduced by 23%.

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A pipelined configurable gate array for embedded processors

Cited by 9 publications

References 14 publications

A Multi-Context Pipelined Array for Embedded Systems

A Multi-Context Pipelined Array for Embedded Systems

Fast prototyping environment for embedded reconfigurable units

Combining low-leakage techniques for FPGA routing design

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