A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application

Mutoh, S.; Shigematsu, Satoshi; Matsuya, Yasuyuki; Fukuda, Hideki; Kaneko, Takao; Yamada, J.

doi:10.1109/jssc.1996.542325

Cited by 60 publications

(32 citation statements)

References 15 publications

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“…Cores are very successful in embedded system design because they reduce design turn-around time by moving all system customization tasks into the software domain. RISC processors are becoming very successful cores [Segars et al 1995;Hasegawa et al [1995], together with specialized processors for digital signal processing [Lee et al 1997b;Mutoh et al 1996;Verbauwhede and Touriguian 1998]. …”

Section: Synthesis Of Computation Unitsmentioning

confidence: 99%

“…Subword parallel instructions [Ishihara and Yasuura 1998b], special addressing modes [Kalambur and Irwin 1997], and native multiply-accumulate instructions [Litch and Slaton 1998] are just a few examples of domain-specific instructions that can reduce power and increase performance when the processor is executing data-dominated applications. Digital signal processors [Mutoh et al 1996;Lee et al 1997b;Verbauwhede and Touriguian 1998] carry this concept to the extreme, providing highly specialized instruction sets. The main problem with this approach is that it is very hard to design compilers that fully exploit the potential of special-ized instructions.…”

Section: Example 42mentioning

confidence: 99%

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System-level power optimization

Benini

Micheli

2000

ACM Trans. Des. Autom. Electron. Syst.

318

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This tutorial surveys design methods for energy-efficient system-level design. We consider electronic systems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods for reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation.This survey is organized around three main phases of a system design: conceptualization and modeling, design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software.

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Section: Synthesis Of Computation Unitsmentioning

confidence: 99%

Section: Example 42mentioning

confidence: 99%

System-level power optimization

Benini

Micheli

2000

ACM Trans. Des. Autom. Electron. Syst.

318

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“…Besides, scaling of transistor dimensions leads to stronger gate leakage and band-to-band tunneling. Leakage power minimization techniques mainly rely on multiple threshold voltage (V th ) CMOS (MTCMOS) [25,26] approach. Power gating which employs the multi-threshold principle, is a popular method of leakage reduction.…”

Section: Introductionmentioning

confidence: 99%

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)

Chowdhury

Khaled

Gjanci

2010

Circuits Syst Signal Process

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Leakage has become one of the most dominant factors of power consumption and signal integrity of nanometer-scale integrated circuits. Recently, powergating structures have proven to be effective in controlling leakage. In this paper an alternative dual-V th reduced power-gating structure is proposed for better reduction of leakage currents, especially for low-power and high-performance portable devices. The proposed technique maintains an intermediate power-saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF modes. In addition, an analysis of ground bounce due to power-mode transition in power-gating structures is presented. It is demonstrated that the proposed technique provides a way to control ground bounce during power-mode transition. Due to the presence of the intermediate state, its stepwise turning on feature will provide higher reduction of the magnitudes of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground as compared to other similar techniques.

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“…Typically, the subthreshold leakage current dominates the device off-state leakage due to low V th transistors employed in logic cell blocks in order to maintain the circuit switching speed in spite of decreasing V DD levels [1]. The MultiThreshold CMOS (MTCMOS) technique can significantly reduce the subthreshold leakage currents during the circuit sleep (standby) mode by adding high-V th power switches (sleep transistors) to low-V th logic cell blocks [2] [3]. This is because the stacked high-V th sleep transistor connected to the bottom of the pull-down network of all logic cells in the circuit acts as a high-resistance element during the sleep mode, which limits the leakage current from V dd to ground lines.…”

Section: Introductionmentioning

confidence: 99%