A 10-bit 100-Msps low power time-interleaved ADC using OTA sharing

Abstract

A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers, and OTA is shared among the channels for low power dissipation. Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing, increasing the accuracy of each channel and global passive sampling respectively. The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement. The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply. Fabricated in a 180-nm CMOS process, the core of the prototype occupies an area of 2.5 1.5 mm 2 , achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.